Datasheet
9Maxim Integrated
16-Bit Microcontrollers with
Infrared Module and Optional USB
MAXQ612/MAXQ622
I
2
C BUS CONTROLLER TIMING
(Notes 6, 21) (Figure 2)
Note 1:
Specifications to 0NC are guaranteed by design and are not production tested.
Note 2:
V
PFW
can be programmed to the following nominal voltage trip points: 1.8V, 1.9V, 2.55V, and 2.75V Q3%. The values
listed in the Recommended Operating Conditions table are for the default configuration of 1.8V nominal.
Note 3:
It is not recommended to write to flash when the supply voltage drops below the power-fail warning levels, as there is
uncertainty in the duration of continuous power supply. The user application should check the status of the power-fail
warning flag before writing to flash to ensure complete write operations.
Note 4: The power-fail warning monitor and the power-fail reset monitor are designed to track each other with a minimum delta
between the two of 0.11V.
Note 5: The power-fail reset and POR detectors are designed to operate in tandem to ensure that one or both of these signals
is active at all times when V
DD
< V
RST
, ensuring the device maintains the reset state until minimum operating voltage is
achieved.
Note 6: Guaranteed by design and not production tested.
Note 7: I
S1
is measured with the USB data RAM powered down.
Note 8: The power-check interval (PCI) can be set to always on, or to 1024, 2048, or 4096 nanopower ring clock cycles.
Note 9: Measured on the V
DD
pin and the device not in reset. All inputs are connected to GND or V
DD
. Outputs do not source/
sink any current. The device is executing code from flash memory.
Note 10: Current consumption during POR when powering up while V
DD
is less than the POR release voltage.
Note 11: The minimum amount of time that V
DD
must be below V
PFW
before a power-fail event is detected.
Note 12: The maximum total current, I
OH(MAX)
and I
OL(MAX)
, for all listed outputs combined should not exceed 25mA to satisfy the
maximum specified voltage drop. This does not include the IRTX output.
Note 13: External clock frequency must be 12MHz to support USB functionality. Full-speed USB(12Mbps)-required bit-rate accu-
racy is Q2500ppm or Q0.25%. This is inclusive of all potential error sources: frequency tolerance, temperature, aging,
crystal capacitive loading, board layout, etc.
Note 14: Programming time does not include overhead associated with utility ROM interface.
PARAMETER SYMBOL
STANDARD MODE FAST MODE
UNITS
MIN MAX MIN MAX
I
2
C Bus Operating Frequency f
I2C
0 100 0 400 kHz
System Frequency f
SYS
0.90 3.60 MHz
I
2
C Bit Rate f
I2C
f
SYS
/8 f
SYS
/8 Hz
Hold Time After (Repeated) START t
HD:STA
4.0 0.6
Fs
Clock Low Period t
LOW_I2C
4.7 1.3
Fs
Clock High Period t
HIGH_I2C
4.0 0.6
Fs
Setup Time for Repeated START t
SU:STA
4.7 0.6
Fs
Hold Time for Data (Notes 22, 23) t
HD:DAT
0 3.45 0 0.9
Fs
Setup Time for Data (Note 24) t
SU:DAT
250 100 ns
SDA/SCL Fall Time (Note 20) t
F_I2C
300 20 + 0.1C
B
300 ns
SDA/SCL Rise Time (Note 20) t
R_I2C
1000 20 + 0.1C
B
300 ns
Setup Time for STOP t
SU:STO
4.0 0.6
Fs
Bus Free Time Between STOP and
START
t
BUF
4.7 1.3
Fs
Capacitive Load for Each Bus Line C
B
400 400 pF
Noise Margin at the Low Level for
Each Connected Device (Including
Hysteresis)
V
nL_I2C
0.1 x V
DD
0.1 x V
DD
V
Noise Margin at the Low Level for
Each Connected Device (Including
Hysteresis)
V
nH_I2C
0.2 x V
DD
0.2 x V
DD
V