Users Guide: MAXQ2010 Supplement User Manual

MAXQ Family User’s Guide:

MAXQ2010 Supplement

21-10

21.2.7 16-Bit Up/Down Count PWM/Output Control Mode

Figure 21-7 shows a functional diagram of the up/down-count PWM/output control mode. When the Timer B PWM/

output control functionality is enabled at the same time as the up/down-count autoreload mode, the TBB pin no longer

controls the direction of counting. Instead, the up/down counting is controlled by logic inside the timer and is deter-

mined by the value of the TBnV count value register. When the timer is counting upward and reaches the value in the

TBnR register, it reverses its direction of counting in the next cycle. When the timer is down counting and reaches

0000h, it reverses direction and begins counting up. This behavior and the results of the TBCS and TBCR bit setting

is shown in Figure 21-8.

The up/down-count PWM duty cycle is calculated as follows (where period = 2 x TBnR Timer B clocks):

Set mode = (TBnR + TBnC)/(2 x TBnR)

Reset mode = TBnC/(2 x TBnR)

Toggle mode = TBnC/TBnR or (TBnR - TBnC)/TBnR

The set and reset up/down-count PWM/output control modes effectively allow 17-bit resolution since set allows duty-

cycle variation R 50% with 50% of the period always being high, and reset allows duty-cycle variation P 50% with 50%

of the period always being low. The toggle mode provides a center-aligned 16-bit PWM with twice the period of the

pure up-counting autoreload mode.

Figure 21-6. Timer B PWM/Output Control Mode Waveform (Count Up)

TBnC > TBnR

TBnC < TBnR

TBnR

0000

TBnC < TBnR

TBCS, TBCR =

TBnC > TBnR

TBCS, TBCR =

TBB PIN

10 (SET)

01 (SET)

11 (TOGGLE)

01 (SET)

11 (TOGGLE)