User guide

13.1 1-Wire Peripheral Registers
The MAXQ microcontroller interfaces to the 1-Wire Bus Master through two peripheral registers: 1-Wire Master Address (OWA) and
1-Wire Master Data (OWD). These two registers allow read/write access of the six internal registers of the 1-Wire Bus Master. The inter-
nal registers provide a means for the CPU to configure and control transmit/receive activity through the Bus Master.
The three least significant bits (A[2:0]) of the OWA peripheral register specify the address of the internal register to be accessed. The
OWD SFR is used for read/write access to the implemented bits of the specified internal register. To access an internal 1-Wire regis-
ter, a valid address must be specified in the OWA peripheral register prior to performing a read/write operation to the OWD peripher-
al register. As long as a valid address is presented in OWA, read accesses of OWD will return data content from the internal target reg-
ister and writes to OWD will update the internal target register with the data provided via OWD (with exception of the interrupt flag
Register, which is read only). The following details the OWA and OWD registers.
13.1.1 1-Wire Address Register (OWA)
Bits 7 to 3: Reserved
Bits 2 to 0: 1-Wire Internal Register Address Bits (A[2:0]). These bits are used to select one of the 1-Wire Master internal registers
to be accessed via the OWD register. Prior to accessing any of the 1-Wire Master internal registers, the address for the target internal
register must be specified. Addresses where A[2:0] = 11xb are considered reserved addresses and ar
e not supported by the Bus
Master. Read access to these addresses will return invalid data in OWD and write accesses will not change the content of any writable
registers.
13.1.2 1-Wire Data Register (OWD)
Bits 7 to 0: 1-Wire Data Register (OWD.[7:0]). This register contains the data value read from the target internal register as selected
by the A[2:0] bits in the OWA register when read. A write to the OWD causes the data to be written to the target internal register select-
ed by the A[2:0] bits of the OWA register (with exception of the interrupt flag register, which is read-only).
13-3
MAXQ Family User’s Guide
Bit #
7 6 5 4 3 2 1 0
Name — — — — — A2 A1 A0
Reset 0 0 0 0 0 1 1 1
Access r r r r r r w r w rw
r = read, w = write
Bit #
7 6 5 4 3 2 1 0
Name OWD.7 O WD.6 OWD.5 OWD.4 OWD.3 OWD.2 OWD.1 OWD.0
Reset 0 0 0 0 0 0 0 0
Access r w r w r w r w r w r w rw r w
r = read, w = write
A2 A1 A0 INTERN A L REGISTER ( READ/ W RI TE AC CESSIBILITY)
0 0 0 Com mand (Read/Write)
0 0 1 Transmit/Receive Buffer (Read/Write)
0 1 0 Inter rupt Flag (Read)
0 1 1 Inter rupt Enable (Read/Write)
1 0 0 Clock Div isor (Read/Write)
1 0 1 Control (Read/Write)
1 1 X Reserved
Maxim Integrated