User guide

2-6
MAXQ Family User’s Guide
2.3 Memory Organization
Beyond the internal register space, memory on the MAXQ microcontroller is organized according to a Harvard architecture, with a sep-
arate address space and bus for program memory and data memory. Stack memory is also separate and is accessed through a ded-
icated register set.
To provide additional memory map flexibility, an MMU allows data memory space to be mapped into a predefined program memory
segment, thus affording the possibility of code execution from data memory. Additionally, program memory space can be made acces-
sible as data space, allowing access to constant data stored in program memory.
2.3.1 Program Memory
Program memory begins at address x0000h and is contiguous through the internal program memory. The actual size of the on-chip
program memory available for user application is product dependent. Given a 16-bit program address bus, the maximum program
space is 64kWords. Since the codewords are 16 bits, the program memory is therefore a 64k x 16 linear space.
Program memory is accessed directly by the program fetching unit and is addressed by the Instruction Pointer register. From an imple-
mentation perspective, system interrupts and branching instructions simply change the contents of the Instruction Pointer and force
the op code fetch from a new program location. The Instruction Pointer is direct read/write accessible by the user software; write access
to the Instruction Pointer will force program flow to the new address on the next cycle following the write. The content of the Instruction
Pointer will be incremented by 1 automatically after each fetch operation. The Instruction Pointer defaults to 8000h, which is the start-
ing address of the utility ROM. The default IP setting of 8000h is assigned to allow initial in-system programming to be accomplished
with utility ROM code assistance. The utility ROM code interrogates a specific register bit in order to decide whether to execute in-sys-
tem programming or jump immediately to user code starting at 0000h. The user code reset vector should always be stored in the low-
est bytes of the program memory.
The program memory is normally implemented using nonvolatile memory, e.g., ROM, EEPROM, or Flash. ROM memory technology
requires program code to be masked into the ROM during chip fabrication; no write access to program memory is available. EEPROM
and Flash provide in-system programming capability but both technologies require that the memory targeted for the write operation be
unprogrammed (erased). The utility ROM provides routines to carry out the necessary operations (erase, write, verify) on these non-
volatile memories.
2.3.2 Utility ROM
A utility ROM is normally placed in the upper 32kWord program memory space starting at address 8000h. This utility ROM potentially
provides the following system utility functions:
• Reset vector
• Bootstrap function for system initialization
• In-application programming
• In-circuit debug
Following each reset, the processor automatically starts execution at address 8000h in the utility ROM, allowing ROM code to perform
any necessary system support functions. Next, the System Programming Enable (SPE) bit is examined to determine whether system
programming should commence or whether that code should be bypassed, instead forcing execution to vector to the start of user pro-
gram code. When the SPE bit is set to logic 1, the processor will execute the prescribed Bootstrap Loader mode program that resides
in utility ROM. The SPE bit defaults to 0. To enter the Bootstrap Loader mode, the SPE bit can be set to 1 during reset via the JTAG
interface. When in-system programming is complete, the Bootstrap Loader can clear the SPE bit and reset the device such that the in-
system programming routine is subsequently bypassed.
2.3.3 Data Memory
On-chip data memory begins at address x0000h and is contiguous through the internal data memory. The actual size of the on-chip
data memory available for the user application is product dependent. Data memory is accessed via indirect register addressing
through a Data Pointer (@DP[n]) or Frame Pointer (@BP[Offs]). The Data Pointer is used as one of the operands in a MOVE instruction.
If the Data Pointer is used as source, the core performs a Load operation that reads data from the data memory location addressed
by the Data Pointer. If the Data Pointer is used as destination, the core executes a Store operation that writes data to the data memo-
ry location addressed by the Data Pointer. The Data Pointer can be directly accessed by the user software.
The core incorporates two 16-bit Data Pointers (DP[0] and DP[1]) to support data memory accessing. All Data Pointers support indi-
rect addressing mode and indirect addressing with auto-increment or auto-decrement. Data Pointers DP[0] and DP[1] can be used as
Maxim Integrated