Datasheet

MAX9880A
Low-Power, High-Performance
Dual I
2
S Stereo Audio Codec
28 ______________________________________________________________________________________
Device Status
Status registers 0x00 and 0x01 are read-only registers
that report the status of various device functions. The
status register bits are cleared upon reading the status
register and are set the next time the event occurs.
Registers 0x02 and 0x03 report the DC level applied to
AUX. See the ADC section for more details.
Bits in status register 0x00 are set when an alert condi-
tion exists. All bits in status register 0x00 are automati-
cally cleared upon a read operation of the register and
are set again if the condition remains or occurs follow-
ing the read of this register.
REGISTER B7 B6 B5 B4 B3 B2 B1 B0
REGISTER
ADDRESS
(SEE NOTE)
POR
STATE
R/W
POWER MANAGEMENT
Enable LNLEN LNREN LOLEN LOREN DALEN DAREN ADLEN ADREN 0x26 0x00 R/W
System Shutdown SHDN 0 0 0 XTEN XTOSC 0 0 0x27 0x00 R/W
REVISION ID
Revision ID REV 0xFF 0x42 R/W
Table 1. Register Map (continued)
* Reserved.
Grayed boxes = Not used.
Note: Register addresses listed are for I
2
C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not
accessible through SPI.
REGISTER B7 B6 B5 B4 B3 B2 B1 B0
REGISTER
ADDRESS
(SEE NOTE)
Status CLD SLD ULK — * * JDET — 0x00
Jack Status JKSNS[1:0] — — — — — — 0x01
AUX High AUX[15:8] 0x02
AUX Low AUX[7:0] 0x03
Table 2. Status Register
* Reserved.
Grayed boxes = Not used.
Note: Register addresses listed are for I
2
C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not
accessible through SPI.