Datasheet

MAX9860
16-Bit Mono Audio Voice Codec
33
Maxim Integrated
Bit Transfer
One data bit is transferred during each SCL cycle. The
data on SDA must remain stable during the high period
of the SCL pulse. Changes in SDA while SCL is high
are control signals (see the START and STOP
Conditions section).
START and STOP Conditions
SDA and SCL idle high when the bus is not in use.
A master initiates communication by issuing a START (S)
condition. A START condition is a high-to-low transition
on SDA with SCL high. A STOP (P) condition is a low-to-
high transition on SDA while SCL is high (Figure 7). A
START condition from the master signals the beginning
of a transmission to the MAX9860. The master terminates
transmission, and frees the bus, by issuing a STOP con-
dition. The bus remains active if a REPEATED START
(Sr) condition is generated instead of a STOP condition.
Early STOP Conditions
The MAX9860 recognizes a STOP condition at any
point during data transmission except if the STOP con-
dition occurs in the same high pulse as a START condi-
tion. For proper operation, do not send a STOP
condition during the same SCL high pulse as the
START condition.
Slave Address
The slave address is defined as the seven most signifi-
cant bits (MSBs) followed by the read/write bit. For the
MAX9860, the seven most significant bits are 0010000.
Setting the read/write bit to 1 (slave address = 0x21)
configures the MAX9860 for read mode. Setting the
read/write bit to 0 (slave address = 0x20) configures
the MAX9860 for write mode. The address is the first
byte of information sent to the MAX9860 after the
START condition.
Acknowledge
The acknowledge bit (ACK) is a clocked 9th bit that the
MAX9860 uses to handshake receipt each byte of data
when in write mode (see Figure 8). The MAX9860 pulls
down SDA during the entire master-generated 9th clock
pulse if the previous byte is successfully received.
Monitoring ACK allows for detection of unsuccessful
data transfers. An unsuccessful data transfer occurs if
a receiving device is busy or if a system fault has
occurred. In the event of an unsuccessful data transfer,
the bus master retries communication. The master pulls
down SDA during the 9th clock cycle to acknowledge
receipt of data when the MAX9860 is in read mode. An
acknowledge is sent by the master after each read byte
to allow data transfer to continue. A not acknowledge is
sent when the master reads the final byte of data from
the MAX9860, followed by a STOP condition.
Write Data Format
A write to the MAX9860 includes transmission of a
START condition, the slave address with the R/W bit set
to 0, one byte of data to configure the internal register
address pointer, one or more bytes of data, and a
STOP condition. Figure 9 illustrates the proper frame
format for writing one byte of data to the MAX9860.
Figure 10 illustrates the frame format for writing n bytes
of data to the MAX9860.
The slave address with the R/W bit set to 0 indicates
that the master intends to write data to the MAX9860.
The MAX9860 acknowledges receipt of the address
byte during the master-generated 9th SCL pulse.
The second byte transmitted from the master config-
ures the MAX9860’s internal register address pointer.
The pointer tells the MAX9860 where to write the next
byte of data. An acknowledge pulse is sent by the
MAX9860 upon receipt of the address pointer data.
SCL
SDA
t
R
t
F
t
BUF
START
CONDITION
STOP
CONDITION
REPEATED START CONDITION
START CONDITION
t
SU,STO
t
HD,STA
t
SU,STA
t
HD,DAT
t
SU,DAT
t
LOW
t
HIGH
t
HD,STA
t
SP
Figure 6. 2-Wire Interface Timing Diagram