Datasheet

SET Voltage Measurement
The SET voltage serves as a reference voltage for the
internal op amp or comparator around which a control
loop can be designed. The low bias current for SET
allows high-impedance resistor-dividers and current out-
put DACs to be used, making it easy to interface without
introducing additional errors.
The SET input can also serve as an auxiliary input port
to the ADC if the op amp or comparator is not utilized in
the application. Its full-scale input range extends from 0V
to 1.10V.
OUT Voltage Measurement
The internal amplifier/comparator output voltage can be
monitored over the entire 0V to 57.3V range by the ADC.
An internal high-value resistor-divider on OUT reduces
leakage current effects.
Common-Mode Voltage Measurement
The input common-mode voltage is defined as the aver-
age of the voltage at RS+ and RS-. A high-value resistor-
divider allows measurement of the input common-mode
voltage over the 0V to 57.3V range.
Sense Voltage Measurement
Three programmable gains allow for a wide range of cur-
rents to be read by the ADC. The current-sense amplifier
gain can be set to 1x, 4x, or 8x. The full-scale sense volt-
ages are then 440mV, 110mV, and 55mV, respectively.
Output Amplier/Comparator
The MAX9611/MAX9612 feature an internally selectable
op amp and comparator where one of the inputs is con-
nected to the 2.5x current-sense amplifier, and the other
input is connected to the SET input. The op amp or the
comparator output can be selected and connected to
OUT. The output stage is an open-drain 60V nFET, that
requires a suitable pullup resistor for proper operation.
The op amp then behaves like a Class-A output stage.
Select op amp or comparator function in Control Register
1 (0x0A) bit 7 (see Tables 4 and 5).
Watchdog/Latch/Retry Functionality
Internal digital circuitry is used to implement a watchdog
feature that can be useful to handle normal application
transients that are not true fault conditions. This feature
applies both to the op amp and comparator modes of
part operation. A watchdog delay time is internally set to
1ms by default but can be changed to 100µs. The retry
delay time is internally set to 50ms by default, but can be
changed to 10ms (see Tables 6 and 7).
In normal operation mode, (Control Register 1 (0x0A)
000x xxxx), the amplifier output responds to the difference
between its inputs, i.e., the CSA output voltage and the
SET voltage. In open-loop configuration, the op amp can
be used as a comparator.
In a watchdog-latch-retry mode (Control Register 1 (0x0A)
111x xxxx), the output of the comparator waits for a
watchdog delay time (to ensure the CSA output continues
to stay above the SET voltage for this duration) before
responding, and then latches onto this state. After a retry
delay time, it resets the comparator state and the cycle
repeats.
Similar functionality is implemented for the op-amp mode
as well (Control Register 1 (0x0A) 000x xxxx to 011x
xxxx).
A RESET bit is defined in Control Register 1 (0x0A) to
reset a latched state when commanded by the user.
I
2
C Interface
The MAX9611/MAX9612 I
2
C interface consists of a
serial-data line (SDA) and serial-clock line (SCL). SDA
and SCL facilitate bidirectional communication between
the MAX9611/MAX9612 and the master at rates up to
400kHz. The MAX9611/MAX9612 are slave devices that
transfer and receive data. The master (typically a micro-
controller) initiates data transfer on the bus and generates
the SCL signal to permit that transfer.
MAX9611/MAX9612 High-Side, Current-Sense Ampliers with
12-Bit ADC and Op Amp/Comparator
www.maximintegrated.com
Maxim Integrated │ 13