Datasheet

PCB Layout Guidelines
Careful PCB layout is important for proper operation. Use
the following guidelines for good PCB layout:
1) Minimize the area of the high current-switching loop
of the rectifier diode, external MOSFET, sense resis-
tor, and output capacitor to avoid excessive switching
noise. Use wide and short traces for the gate-drive
loop from the EXT pin, to the MOSFET gate, and
through the current-sense resistor, then returning to
the IC GND pin.
2) Connect high-current input and output components
with short and wide connections. The high-current
input loop goes from the positive terminal of the input
capacitor to the inductor, to the external MOSFET,
then to the current-sense resistor, and to the input
capacitor’s negative terminal. The high-current output
loop is from the positive terminal of the input capacitor
to the inductor, to the rectifier diode, to the positive ter-
minal of the output capacitors, reconnecting between
the output capacitor and input capacitor ground termi-
nals. Avoid using vias in the high-current paths. If vias
are unavoidable, use multiple vias in parallel to reduce
resistance and inductance.
3) Create a ground island (PGND) consisting of the input
and output capacitor ground and negative terminal of
the current-sense resistor. Connect all these together
with short, wide traces or a small ground plane.
Maximizing the width of the power ground traces
improves efficiency and reduces output-voltage ripple
and noise spikes. Create an analog ground island
(AGND) consisting of the overvoltage detection-divider
ground connection, the ISET and FSET resistor con-
nections, CCV and CPLL capacitor connections, and
the device’s exposed backside pad. Connect the
AGND and PGND islands by connecting the GND pins
directly to the exposed backside pad. Make no other
connections between these separate ground planes.
4) Place the overvoltage detection-divider resistors as
close to the OV pin as possible. The divider’s center
trace should be kept short. Placing the resistors far
away causes the sensing trace to become antennas
that can pick up switching noise. Avoid running the
sensing traces near LX.
5) Place the IN pin bypass capacitor as close to the
device as possible. The ground connection of the IN
bypass capacitor should be connected directly to GND
pins with a wide trace.
6) Minimize the size of the LX node while keeping it wide
and short. Keep the LX node away from the feedback
node and ground. If possible, avoid running the LX
node from one side of the PCB to the other. Use DC
traces as shields, if necessary.
7) Refer to the MAX8790A evaluation kit for an example
of proper board layout.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE NO.
LAND
PATTERN
NO.
20 TQFN-EP T2044+3 21-0139 90-0037
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character,
but the drawing pertains to the package regardless of RoHS
status.
19
20
18
17
7
6
8
ENA
FB1
9
OSC
OV CS FB6 V
CC
1 2
ISET
4 5
15 14 12 11
FSET
CPLL
FB4
GND
FB3
FB2
MAX8790AETP+
BRT
EXT
3
13
CCV
16
10
FB5
IN
4mm x 4mm THIN QFN
TOP VIEW
SHDN
MAX8790A Six-String White LED Driver with Active
Current Balancing for LCD Panel Applications
www.maximintegrated.com
Maxim Integrated │ 21
Pin Conguration
Chip Information
PROCESS: BiCMOS