Datasheet

MAX817L/M, MAX818L/M, MAX819L/M*
+5V Microprocessor Supervisory Circuits
_______________________________________________________________________________________ 7
______________________________________________________________Pin Description
Ground. 0V reference for all signals.33
Input Supply Voltage, +5V input.22
Supply Output for CMOS RAM. When V
CC
rises above the reset threshold
or above V
BATT
, OUT is connected to V
CC
through an internal P-channel
MOSFET switch. When V
CC
falls below V
BATT
, BATT connects to OUT.
11
GND3
V
CC
2
OUT1
Power-Fail Comparator Output. When PFI is less than V
PFT
or when V
CC
is
below V
BATT
, PFO goes low; otherwise PFO remains high. PFO is also used to
enable the battery freshness seal (see Battery Freshness Seal and Power-Fail
Comparator sections).
—5
Chip-Enable Input. The input to the chip-enable gating circuit. Connect to
ground if unused.
4—
Power-Fail Comparator Input. When V
PFI
is below V
PFT
or when V
CC
is below
V
BATT
, PFO goes low; otherwise, PFO remains high (see Power-Fail Comparator
section). Connect to ground if unused.
—4
PFO
5
CE IN
—
PFI4
Backup-Battery Input. When V
CC
falls below V
BATT
, OUT switches from V
CC
to
BATT. When V
CC
rises above V
BATT
, OUT reconnects to V
CC
.
88
Active-Low Reset Output. Pulses low for 200ms when triggered and remains
low whenever V
CC
is below the reset threshold or when MR is a logic low. It
remains low for 200ms after V
CC
rises above the reset threshold, the watchdog
triggers a reset, or MR goes low to high.
77
BATT8
RESET
7
Manual Reset Input. A logic low on MR asserts reset. Reset remains asserted
for as long as MR is held low and for 200ms after MR returns high. The active-
low input has an internal 63kΩ pull-up resistor. It can be driven from a TTL- or
CMOS-logic line or shorted to ground with a switch. Leave open, or connect to
V
CC
if unused.
——
Watchdog Input. If WDI remains either high or low for longer than the watch-
dog timeout period, the internal watchdog timer runs out and a reset is trig-
gered. If WDI is left unconnected or is connected to a high-impedance
three-state buffer, the watchdog feature is disabled. The internal watchdog
timer clears whenever reset is asserted, WDI is three-stated, or WDI sees a ris-
ing or falling edge. The WDI input is designed to be driven by a three-stated-
output device with a maximum high-impedance leakage current of 10µA and a
maximum output capacitance of 200pF. The output device must also be capa-
ble of sinking and sourcing 200µA when active.
66
Chip-Enable Output. CE OUT goes low only if CE IN is low while reset is not
asserted. If CE IN is low when reset is asserted, CE OUT will remain low for
15µs or until CE IN goes high, whichever occurs first. CE OUT is pulled up to
OUT in battery-backup mode. CE OUT is also used to enable the battery
freshness seal (see Battery Freshness Seal section).
5—
MR
6
WDI—
CE OUT
—
FUNCTIONNAME
MAX817 MAX818 MAX819
PIN