Datasheet
MAX814/MAX815/MAX816
where C
HOLD
is the capacitance (in Farads), I
LOAD
is
the current being drained from the capacitor (in
Amperes), and V
LR
is the low-line to reset threshold dif-
ference (in Volts).
Manual Reset
Many µP-based products require manual-reset capabil-
ity, allowing the operator, a test technician, or external
logic circuitry to initiate a reset. A logic low on MR
asserts reset. Reset remains asserted while MR is low,
and for t
RS
(200ms) after MR returns high. This input
has an internal pullup resistor, so it can be left open if
not used. MR can be driven with TTL/CMOS-logic lev-
els or with open-drain/collector outputs.
Connect a normally open momentary switch from MR to
GND to create a manual-reset function; external
debounce circuitry is not required.
The watchdog circuit can be used to force a reset in
the MAX815 by connecting WDO to MR. If MR is driven
from long cables, or the device is used in a noisy envi-
ronment, connect a 0.1µF capacitor to ground to pro-
vide additional noise immunity.
__________Applications Information
Low-Voltage Operation
The LOW LINE, PFO, and WDO outputs will be locked to
logic low when the power supply drops below the lock-
out threshold (typically 1V below the reset threshold).
Ensuring a Valid
RESET
Output Down to V
CC
= 0V
When V
CC
falls below 1V, the RESET output no longer
sinks current, but becomes an open circuit. High-
impedance CMOS-logic inputs can drift to undeter-
mined voltages if left undriven. If a pulldown resistor is
added to the RESET pin as shown in Figure 10, any
stray charge or leakage currents will be drained to
ground, holding RESET low. Resistor value R1 is not
critical. It should be about 100kΩ—large enough not to
load RESET, and small enough to pull RESET to
ground.
±1% Accuracy, Low-Power, +3V and +5V
µP Supervisory Circuits
12 ______________________________________________________________________________________
Figure 9. Timing Diagram
∆V
LL
V
CC
0
0
0
V
CC
V
CC
V
CC
V
LLT
60mV
V
RT
V
RT
t
RS
t
MR
t
MD
t
RS
LOW LINE
(MAX814)
WDO
(MAX815)
MR
RESET
Figure 8. MAX815 Watchdog Timing
V
CC
0V
V
CC
0V
V
CC
0V
V
CC
0V
MR
WDI
WDO
RESET
RESET
t
WD
t
WP
t
WD
t
WD
t
WDO