Datasheet

Alternatively, MAX7317s can be daisy-chained by
connecting the DOUT of one device to the DIN of the
next, and driving SCLK and CS lines in parallel (Figure 3).
This connection allows the MAX7317s to be read. Data
at DIN propagates through the internal shift registers and
appears at DOUT 15.5 clock cycles later, clocked out on
the falling edge of SCLK. When sending commands to
daisy-chained MAX7317s, all devices are accessed at
the same time. An access requires (16 x n) clock cycles,
where n is the number of MAX7317s connected together.
The serial interface speed (maximum SCLK) is limited to
10MHz when multiple devices are daisy-chained due to
the DOUT propagation delay and DIN setup time.
The MAX7317 is written to using the following sequence
(Figure 5):
1) Take SCLK low.
2) Take CS low. This enables the internal 16-bit shift
register.
3) Clock 16 bits of data into DIN, D15 first to D0 last,
observing the setup and hold times. Bit D15 is low,
indicating a write command.
4) Take CS high (either while SCLK is still high after
clocking in the last data bit, or after taking SCLK low).
5) Take SCLK low (if not already low).
If fewer or greater than 16 bits are clocked into the
MAX7317 between taking CS low and taking CS high
again, the MAX7317 stores the last 16 bits received,
including the previous transmission(s). The general case
is when n bits (where n > 16) are transmitted to the
MAX7317. The last bits comprising bits {n-15} to {n}, are
retained, and are parallel loaded into the 16-bit latch as
bits D15 to D0, respectively (Figure 6).
Reading Device Registers
Any register data within the MAX7317 can be read by
sending a logic high to bit D15. The sequence is:
1) Take SCLK low.
2) Take CS low. This enables the internal 16-bit shift
register.
3) Clock 16 bits of data into DIN, D15 first to D0 last.
D15 is high, indicating a read command and bits
D14 through D8 contain the address of the register
to read. Bits D7 to D0 contain dummy data, which is
discarded.
4) Take CS high (either while SCLK is still high after
clocking in the last data bit, or after taking SCLK low).
Positions D7 through D0 in the shift register are now
loaded with the register data addressed by bits D15
through D8.
5) Take SCLK low (if not already low).
6) Issue another read or write command, and exam-
ine the bit stream at DOUT; the second 8 bits are
the contents of the register addressed by bits D14
through D8 in step 3.
Figure 2. MAX7317 Multiple CS Connection
Table 5. Serial-Data Format
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
R/W MSB ADDRESS LSB MSB DATA LSB
DIN
SCLK
CS3
DIN
SCLK
CS2
DIN
SCLK
MOSI
SCLK
CS1
CS3
CS2
CS1
MAX7317MAX7317MAX7317
µC
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MAX7317 10-Port SPI-Interfaced I/O Expander with
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