Datasheet

MAX6950/MAX6951
be unable to regulate the current correctly. As the sup-
ply voltage drops further, the LED segment drive cur-
rent becomes effectively limited by the output drivers'
on-resistance, and the LED drive current drops. The
characteristics of each individual LED in a modern 7-
segment digit usually match well, so the result is that
the display intensity dims uniformly as supply voltage
drops out of regulation and beyond. The MAX6950/
MAX6951 operate down to 2V supply voltage (although
most displays are very dim at this voltage), providing
that the MAX6950/MAX6951 are powered up initially to
at least 2.7V to trigger the device's internal reset, and
also that the SPI interface is constrained to 5Mbps.
Computing Power Dissipation
The upper limit for power dissipation (PD) for the
MAX6950/MAX6951 is determined from the following
equation:
P
D
= (V+ x I+) + (V+ - V
LED
) (DUTY
✕
I
SEG
✕
N)
Where:
V+ = supply voltage
DUTY = duty cycle set by intensity register
N = number of segment driven (worst case is 8)
V
LED
= LED forward voltage
I
SEG
= segment current set by R
SET
PD = power dissipation, in mW if currents are in mA
Dissipation example:
I
SEG
= 40mA, N = 8, Duty = 15/16, V
LED
= 2.4V at
40mA, V+ = 3.6V
P
D
= 3.6V (15mA) + (3.6V - 2.4V)(15 / 16
✕
40mA x 8)
= 0.414W
Thus, for the 16-pin QSOP package (T
JA
= 1/0.00834 =
+120°C/W), the maximum allowed ambient temperature
T
A
is given by:
T
J (MAX)
= T
A
+ (P
D
✕
T
JA
) = +150°C = T
A
+ (0.44
✕
+120°C/W)
So T
A
= +100°C. Thus, the device can be operated
safely at a maximum package temperature of +85°C.
Power Supplies
The MAX6950/MAX6951 operate from a single +2.7V to
+5.5V power supply. Bypass the power supply to
ground with a 0.1µF capacitor as close to the pin as
possible. Add a 22µF capacitor if the MAX6950/
MAX6951 are not close to the board’s input bulk decou-
pling capacitor.
Connect the underside exposed pad to GND.
Board Layout
When designing a board, use the following guidelines:
1. The R
SET
connection to pin 7 is a high-impedance
node, and sensitive to layout. Place R
SET
right next
to pins 7 and 8 and route R
SET
directly to these pins
with very short tracks.
2. Ensure that the track from the ground end of R
SET
routes directly to pin 8, and that this track is not
used as part of any other ground connection.
Figure 5 shows a good layout. The decoupling capaci-
tors C1 (ceramic) and C2 (bulk, if required) are located
above the IC. The ground track to R
SET
is a separate
track from both the IC's power ground connection and
the ground plane.
Serially Interfaced, +2.7V to +5.5V,
5- and 8-Digit LED Display Drivers
16 ______________________________________________________________________________________
Table 17. Digit Register Mapping with
Blink Globally Disabled
SEGMENT’S
BIT SETTING
IN PLANE P1
SEGMENT’S
BIT SETTING
IN PLANE P0
SEGMENT
BEHAVIOR
X0
Segment off during both
halves of each blink
period
X1
Segment off during both
halves of each blink
period
Table 18. Digit Register Mapping with
Blink Globally Enabled
SEGMENT’S
BIT SETTING
IN PLANE P1
SEGMENT’S
BIT SETTING
IN PLANE P0
SEGMENT
BEHAVIOR
0 0 Segment off
01
Segment on only during
the 1st half of each blink
period
10
Segment on only during
the 2nd half of each blink
period
1 1 Segment on