Datasheet

MAX667
+5V/Programmable Low-Dropout
Voltage Regulator
_______________________________________________________________________________________ 3
1000
1
1 10 100 1000
DROPOUT VOLTAGE
vs. LOAD CURRENT
10
100
MAX667-Fg TOC 1
LOAD CURRENT (mA)
DROPOUT VOLTAGE (mV)
QUIESCENT CURRENT
vs. LOAD CURRENT
QUIESCENT CURRENT (μA)
10
100
1000
10,000
100,000
0.01 0.1 1 10 100 1000
MAX667-Fg TOC 2
LOAD CURRENT (mA)
V
IN
= +6V
1000
1
0 50 150 250
10
100
MAX667-Fg TOC 3
100 200
DD OUTPUT CURRENT
vs. INPUT-OUTPUT DIFFERENCE
DD OUTPUT CURRENT (μA)
INPUT-OUTPUT DIFFERENCE (mV)
5 10
1
20 50 100mA LOAD
2
__________________________________________Typical Operating Characteristics
_____________________Pin Description _______________Detailed Description
Figure 1 shows a micropower bandgap reference, an
error amplifier, a PNP pass transistor, and two com-
parators as the main elements of the MAX667. One
comparator, C1, selects the fixed 5V or adjustable
operation with an external voltage divider. The other
comparator, C2, is a low-battery detector.
The bandgap reference, which is trimmed to 1.22V,
connects internally to one input of the error amplifier,
A1. The feedback signal from the regulator output sup-
plies the other input of A1 from either an on-chip volt-
age divider or two external resistors. When SET is
grounded, the internal divider provides the error ampli-
fier feedback signal for a fixed 5V output. When SET is
more than 50mV above ground, the error amplifier’s
input switches directly to SET while an external resistor
divider from OUT determines the output voltage.
A second comparator, C2, compares the LBI input to
the internal reference voltage. LBO is an open-drain
FET connected to GND. The low-battery threshold can
also be set with a voltage divider at LBI. In addition, the
MAX667 has a shutdown input (SHDN) that disables
the load and the device while reducing quiescent cur-
rent when it is pulled high.
+5V Output
Figure 2 shows the connection for a fixed 5V output.
The SET input is grounded, and no external resistors
are required. Figure 3 shows adjustable output opera-
tion. R1 and R2 set the output voltage. SHDN should be
grounded if not used.
(Output) Voltage Set, CMOS Input.
Connect to GND for 5V output. For
other voltages, connect external resis-
tive divider from OUT.
SET6
Low-Battery Output. An open-drain N-
channel transistor that sinks current to
GND when LBI is less than 1.22V.
LBO7
Positive Input Voltage (unregulated)IN8
Regulated Output Voltage. OUT falls
to 0V when SHDN is above 1.5V. SET
determines output voltage when SET
is above 50mV; otherwise, it is 5V.
OUT must be connected to an output
filter capacitor.
OUT2
Low-Battery Detector. A CMOS input
to an internal 1.255V comparator
whose output is the LBO pin.
LBI3
GroundGND4
Shutdown Input. Connect to GND for
normal operation (output active). Pull
above 1.5V to disable OUT, LBO, and
DD and to reduce quiescent current to
less than 1µA.
SHDN5
PIN
Dropout Detector Output—the collec-
tor of a PNP pass transistor. Normally
an open circuit, it sources current as
dropout is reached.
DD1
FUNCTIONNAME
(T
A
= +25°C, unless otherwise noted.)