Datasheet
MAX6365–MAX6368
SOT23, Low-Power µP Supervisory Circuits
with Battery Backup and Chip-Enable Gating
8 _______________________________________________________________________________________
MAX6365
MAX6366
MAX6367
MAX6368
CHIP-ENABLE
OUTPUT
CONTROL
V
CC
BATT
CE IN
20k
MR
(MAX6365 ONLY)
WDI
(MAX6366 ONLY)
RESET IN
(MAX6368 ONLY)
RESET
GENERATOR
WATCHDOG
TRANSITION
DETECTOR
WATCHDOG
TIMER
1.235V
GND
1.235V
RESET
(RESET)
CE OUT
OUT
BATT ON (MAX6367 ONLY)
Detailed Description
The
Typical Operating Circuit
shows a typical connec-
tion for the MAX6365–MAX6368. OUT powers the static
random-access memory (SRAM). If V
CC
is greater than
the reset threshold (V
TH
), or if V
CC
is lower than V
TH
but higher than V
BATT
, V
CC
is connected to OUT. If
V
CC
is lower than V
TH
and V
CC
is less than V
BATT
,
BATT is connected to OUT. OUT supplies up to 150mA
from V
CC
. In battery-backup mode, an internal MOSFET
connects the backup battery to OUT. The on-resistance
of the MOSFET is a function of backup-battery voltage
and is shown in the BATT-to-OUT On-Resistance vs.
Temperature graph in the
Typical Operating Char-
acteristics
.
Chip-Enable Signal Gating
The MAX6365–MAX6368 provide internal gating of CE
signals to prevent erroneous data from being written to
CMOS RAM in the event of a power failure. During nor-
mal operation, the CE gate is enabled and passes all
CE transitions. When reset asserts, this path becomes
disabled, preventing erroneous data from corrupting
the CMOS RAM. All of these devices use a series trans-
mission gate from CE IN to CE OUT. The 2ns propaga-
tion delay from CE IN to CE OUT allows the devices to
be used with most µPs and high-speed DSPs.
During normal operation, CE IN is connected to CE
OUT through a low on-resistance transmission gate.
This is valid when reset is not asserted. If CE IN is high
when reset is asserted, CE OUT remains high regard-
less of any subsequent transitions on CE IN during the
reset event.
If CE IN is low when reset is asserted, CE OUT is held
low for 12µs to allow completion of the read/write oper-
ation (Figure 1). After the 12µs delay expires, the CE
Functional Diagram