Datasheet

watchdog counter. When WDI is left unconnected, the
watchdog timer is cleared by this internal driver just
before the timeout period is reached (the internal driver
pulls WDI high at about 94% of t
WD
). When WDI is
three-stated, the maximum allowable leakage current of
the device driving WDI is 10µA.
In normal mode (WDS = GND), the watchdog timer
cannot be disabled by three-stating WDI. WDI is a
high-impedance input in this mode. Do not leave WDI
unconnected in normal mode.
Applications Information
Selecting the Reset and Watchdog
Timeout Capacitor
The reset timeout period is adjustable to accommodate
a variety of µP applications. Adjust the reset timeout
period (t
RP
) by connecting a specific value capacitor
(C
SRT
) between SRT and ground (Figure 3). Calculate
the reset timeout capacitor as follows:
C
SRT
= t
RP
/2.67
MAX6301–MAX6304
+5V, Low-Power µP Supervisory Circuits
with Adjustable Reset/Watchdog
_______________________________________________________________________________________ 7
V
CC
V
CC
0V
0V
WDI
RESET
NORMAL MODE (WDS = GND)
t
WD
t
RP
V
CC
V
CC
0V
0V
WDI
RESET
EXTENDED MODE (WDS = V
CC
)
t
WD
x 500 t
RP
Figure 2a. Watchdog Timing Diagram, WDS = GND
Figure 2b. Watchdog Timing Diagram, WDS = V
CC
0.1µF
MAX6301
MAX6302
MAX6303
MAX6304
V
CC
GND
C
SRT
=
t
RP
2.67
V
CC
C
SWT
C
SRT
C
SRT
in pF
t
RP
in µs
C
SWT
=
t
WD
2.67
C
SWT
in pF
t
WD
in µs
SRT
SWT
Figure 3. Calculating the Reset (C
SRT
) and Watchdog (C
SWT
)
Timeout Capacitor Values