Datasheet

MAX6301–MAX6304
with C
SRT
in pF and t
RP
in µs. C
SRT
must be a low-leak-
age (< 10nA) type capacitor. Ceramic is recommended.
The watchdog timeout period is adjustable to accom-
modate a variety of µP applications. With this feature,
the watchdog timeout can be optimized for software
execution. The programmer can determine how often
the watchdog timer should be serviced. Adjust the
watchdog timeout period (t
WD
) by connecting a specif-
ic value capacitor (C
SWT
) between SWT and ground
(Figure 3). For normal-mode operation, calculate the
watchdog timeout capacitor as follows:
C
SWT
= t
WD
/2.67
where C
SWT
is in pF and t
WD
is in µs. C
SWT
must be a
low-leakage (< 10nA) type capacitor. Ceramic is
recommended.
Monitoring Voltages Other than V
CC
The Typical Operating Circuit monitors V
CC
. Voltages
other than V
CC
can easily be monitored, as shown in
Figure 4. Calculate V
RST
as shown in the Reset
Threshold
section.
Wake-Up Timer
In some applications, it is advantageous to put a µP
into sleep mode, periodically wake it up to perform
checks and/or tasks, then put it back into sleep mode.
The MAX6301 family of supervisors can easily accom-
modate this technique. Figure 5 illustrates an example
using the MAX6302 and an 80C51.
In Figure 5, just before the µC puts itself into sleep
mode, it pulls WDS high. The µC’s I/O pins maintain
their logic levels while in sleep mode and WDS remains
high. This places the MAX6302 in extended mode,
increasing the watchdog timeout 500 times. When the
watchdog timeout period ends, a reset is applied on
the 80C51, waking it up to perform tasks. While the µP
is performing tasks, the 80C51 pulls WDS low (select-
ing normal mode), and the MAX6302 monitors the µP
for hang-ups. When the µP finishes its tasks, it puts
itself back into sleep mode, drives WDS high, and
starts the cycle over again. This is a power-saving tech-
nique, since the µP is operating only part of the time
and the MAX6302 has very low quiescent current.
Adding a Manual Reset Function
A manual reset option can easily be implemented by con-
necting a normally open momentary switch in parallel with
R2 (Figure 6). When the switch is closed, the voltage on
RESET IN goes to zero, initiating a reset. When the
switch is released, the reset remains asserted for the
reset timeout period and then is cleared. The pushbut-
ton switch is effectively debounced by the reset timer.
+5V, Low-Power µP Supervisory Circuits
with Adjustable Reset/Watchdog
8 _______________________________________________________________________________________
0.1µF
MAX6301
MAX6302
MAX6303
MAX6304
V
CC
RESET IN
R2
R1
V
IN
V
RST
= 1.22
(
R1 + R2
)
R2
V
CC
Figure 4. Monitoring Votlages Other than V
CC
MAX6302
V
CC
RESET
WDI
WDS
V
CC
I/O
I/O
I/O
GND
80C51
V
CC
V
CC
GND
RST
*THREE-STATE LEAKAGE MUST BE < 10µA.
*
Figure 5. Wake-Up Timer
0.1µF
MAX6301
MAX6302
MAX6303
MAX6304
V
CC
RESET IN
R2
R1
V
CC
Figure 6. Adding a Manual Reset Function