Datasheet

MAX618
28V, PWM, Step-Up DC-DC Converter
10 ______________________________________________________________________________________
Maximum Output Current
The MAX618’s 2.2A LX current limit determines the
output power that can be supplied for most applica-
tions. In some cases, particularly when the input volt-
age is low, output power is sometimes restricted by
package dissipation limits. The MAX618 is protected
by a thermal shutdown circuit that turns off the switch
when the die temperature exceeds +150°C. When the
device cools by 10°C, the switch is enabled again.
Table 3 details output current with a variety of input and
output voltages. Each listing in Table 3 is either the limit
set by an LX current limit or by package dissipation at
+85°C ambient, whichever is lower. The values in Table
3 assume a 40mΩ inductor resistance.
Capacitor Selection
Input Capacitors
The input bypass capacitor, C
IND
, reduces the input
ripple created by the boost configuration. High-imped-
ance sources require high C
IND
values. However, 68μF
is generally adequate for input currents up to 2A. Low
ESR capacitors are recommended because they will
decrease the ripple created on the input and improve
efficiency. Capacitors with ESR below 0.3Ω are gener-
ally appropriate.
In addition to the input bypass capacitor, bypass IN
with a 1μF ceramic capacitor placed as close to the IN
and GND pins as possible. Bypass VL with a 4.7μF
ceramic capacitor placed as close to the VL and GND
pins as possible.
Output Capacitor
Use Table 4 to find the minimum output capacitance
necessary to ensure stable operation. In addition,
choose an output capacitor with low ESR to reduce the
output ripple. The dominant component of output ripple
is the product of the peak-to-peak inductor ripple cur-
rent and the ESR of the output capacitor. ESR below
50mΩ generates acceptable levels of output ripple for
most applications.
Integrator Capacitor
The compensation capacitor (C
COMP
) sets the domi-
nant pole in the MAX618’s transfer function. The proper
compensation capacitance depends upon output
capacitance. Table 5 shows the capacitance value
needed for the output capacitances specified in Table
4. However, if a different output capacitor is used (e.g.,
a standard value), then recalculate the value of capaci-
tance needed for the integrator capacitor with the fol-
lowing formula:
Pole Compensation Capacitor
The pole capacitor (C
P
) cancels the unwanted zero
introduced by C
OUT
’s ESR, and thereby ensures stabil-
ity in PWM operation. The exact value of the pole
capacitor is not critical, but it should be near the value
calculated by the following equation:
where R
ESR
is C
OUT
’s ESR.
Layout Considerations
Proper PC board layout is essential due to high current
levels and fast switching waveforms that radiate noise.
Use the MAX618 evaluation kit or equivalent PC layout
to perform initial prototyping. Breadboards, wire-wrap,
and proto-boards are not recommended when proto-
typing switching regulators.
It is important to connect the GND pin, the input
bypass capacitor ground lead, and the output filter
capacitor ground lead to a single point to minimize
ground noise and improve regulation. Also, minimize
lead lengths to reduce stray capacitance, trace resis-
tance, and radiated noise, with preference given to the
feedback circuit, the ground circuit, and LX. Place the
feedback resistors as close to the FB pin as possible.
Place a 1μF input bypass capacitor as close as possi-
ble to IN and GND.
Refer to the MAX618 evaluation kit for an example of
proper board layout.
Chip Information
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns,
go to www.maxim-ic.com/packages
. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package
drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
C
RC(R1R2)
R1 R2
P
ESR OUT
=
+
⋅
⋅
C
C Table C
C Table
COMP
COMP OUT
OUT
=
⋅()
()
5
4
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
16 QSOP EF16+8F
21-0055