Datasheet

MAX5986A–MAX5986C/MAX5987A
IEEE 802.3af-Compliant, High-Efficiency, Class 1/
Class 2, PDs with Integrated DC-DC Converter
7Maxim Integrated
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 48V, R
SIG
= 24.9kω, LED, V
CC
, SL, ULP, WK, RESET, LDO_OUT unconnected, WAD = LDO_EN = LDO_IN = PGND = GND,
C1 = 68nF, C2 = 10µF, C3 = 1µF (see Figure 3), V
FB
= V
AUX
= 0V, LX unconnected. All voltages are referenced to GND, unless
otherwise noted. T
A
= T
J
= -40°C to +85°C, unless otherwise noted. Typical values are at T
A
= +25°C.) (Note 3)
Note 3: All devices are 100% production tested at T
A
= +25°C. Limits over temperature are guaranteed by design.
Note 4: The input offset current is illustrated in Figure 2.
Note 5: Effective differential input resistance is defined as the differential resistance between V
DD
and GND, see Figure 2.
Note 6: A 20V glitch on input voltage, which takes V
DD
below V
ON
shorter than or equal to t
OFF_DLY
does not cause the device to
exit power-on mode.
Note 7 Referred to feedback regulation voltage.
Note 8: Referred to LDO feedback regulation voltage.
Note 9: The WAD Detection Rising and Falling Thresholds control the isolation power MOS transistor. To turn the DC-DC on in
WAD mode, the WAD must be detected and the V
DD
must be within the V
DD
voltage range.
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
RESET (MAX5987A)
V
FB
Threshold for RESET Assertion
V
FB-OKF
V
FB
falling (Note 7) 87 90 93 %
V
FB
Threshold for RESET
Deassertion
V
FB-OKR
V
FB
rising (Note 7) 91.5 95 98 %
V
LDO_FB
Threshold for RESET
Assertion
V
LDO_FB-OKF
V
LDO_FB
falling, LDO_FB = V
DRV
(Note 8)
90 %
V
LDO_FB
Threshold for RESET
Deassertion
V
FB
rising 95 %
for RESET Deassertion Delay 4.8 ms
RESET Output Voltage Low I
SINK
= 1mA 0.1 V
RESET Leakage Current ±10 FA