Datasheet

MAX5888
3.3V, 16-Bit, 500Msps High Dynamic
Performance DAC with Differential LVDS Inputs
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(AV
DD
= DV
DD
= VCLK = 3.3V, AGND = DGND = CLKGND = 0, external reference, V
REFIO
= 1.25V, differential transformer-coupled
analog output, 50Ω double terminated (Figure 7), I
OUT
= 20mA, T
A
= T
MIN
to T
MAX
, unless otherwise noted. ≥+25°C guaranteed by
production test, <+25°C guaranteed by design and characterization. Typical values are at T
A
= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
TIMING CHARACTERISTICS
Data to Clock Setup Time t
SETUP
Referenced to rising edge of clock (Note 4) -0.8
ns
Data to Clock Hold Time t
HOLD
Referenced to rising edge of clock (Note 4)
1.8 ns
Data Latency 3.5
Clock
cycles
Minimum Clock Pulse Width High
t
CH
CLKP, CLKN 0.9 ns
Minimum Clock Pulse Width Low
t
CL
CLKP, CLKN 0.9 ns
LVDS LOGIC INPUTS (B0N–B15N, B0P–B15P)
Differential Input Logic High V
IH
100
mV
Differential Input Logic Low V
IL
-100
mV
Common-Mode Voltage Range V
COM
1.125 1.375
V
Differential Input Resistance R
IN
85
100
125 Ω
Input Capacitance C
IN
5pF
CMOS LOGIC INPUTS (PD, SEL0)
Input Logic High V
IH
0.7 ✕
DV
DD
V
Input Logic Low V
IL
0.3 ✕
DV
DD
V
Input Leakage Current I
IN
-15 +15 µA
Input Capacitance C
IN
5pF
CLOCK INPUTS (CLKP, CLKN)
Sine wave
≥1.5
Differential Input Voltage Swing V
CLK
Square wave
≥0.5
V
P-P
Differential Input Slew Rate SR
CLK
(Note 5)
>100
V/µs
Common-Mode Voltage Range V
COM
1.5
±20%
V
Input Resistance R
CLK
5kΩ
Input Capacitance C
CLK
5pF
POWER SUPPLIES
Analog Supply Voltage Range AV
DD
3.135
3.3
3.465
V
Digital Supply Voltage Range DV
DD
3.135
3.3
3.465
V
Clock Supply Voltage Range V
CLK
3.135
3.3
3.465
V
f
CLK
= 100Msps, f
OUT
= 1MHz 27
Analog Supply Current I
AVDD
Power-down 0.3
mA
f
CLK
= 100Msps, f
OUT
= 1MHz 7 mA
Digital Supply Current I
DVDD
Power-down 10 µA
f
CLK
= 100Msps, f
OUT
= 1MHz 5.6 mA
Clock Supply Current I
VCLK
Power-down 10 µA