Datasheet

MAX5742
12-Bit, Low-Power, Quad, Voltage-Output
DAC with Serial Interface
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= +2.7V to +5.5V, GND = 0, V
REF
= V
DD
, R
L
= 5kΩ, C
L
= 200pF, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are
V
DD
= +5V, T
A
= +25°C.)
TIMING CHARACTERISTICS
(V
DD
= 2.7V to 5.5V, GND = 0, T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
Note 1: DC specifications are tested without output loads.
Note 2: Linearity guaranteed from code 115 to code 3981.
Note 3: Limited with test conditions.
Note 4: Offset and gain error limit the FSR.
Note 5: Guaranteed by design.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DIGITAL INPUTS (SCLK, DIN, CS)
Input High Voltage V
IH
V
DD
= +3V, +5V
0.7 x
V
DD
V
Input Low Voltage V
IL
V
DD
= +3V, +5V
0.3 x
V
DD
V
Input Leakage Current I
IN
Digital inputs = 0 or V
DD
±0.1 ±1µA
Input Capacitance C
IN
5pF
DYNAMIC PERFORMANCE
Voltage Output Slew Rate SR 0.5 V/µs
Voltage Output Settling Time 400 hex to C00 hex (Note 5) 4 10 µs
Digital Feedthrough Any digital inputs from 0 to V
DD
0.1 nV-s
Digital-Analog Glitch Impulse
Major carry transition (code 7FF hex to code
800 hex)
12 nV-s
DAC-to-DAC Crosstalk 2.4 nV-s
POWER REQUIREMENTS
Supply-Voltage Range V
DD
2.7 5.5 V
All digital inputs at 0 or V
DD
= 3.6V 229 395
Supply Current with No Load I
DD
All digital inputs at 0 or V
DD
= 5.5V 271 420
µA
Power-Down Supply Current I
DDPD
All digital inputs at 0 or V
DD
= 5.5V 0.29 1 µA
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SCLK Clock Frequency f
SCLK
0 20 MHz
SCLK Pulse Width High t
CH
25 ns
SCLK Pulse Width Low t
CL
25 ns
CS Fall to SCLK Rise Setup Time t
CSS
10 ns
SCLK Fall to CS Rise Setup Time t
CSH
10 ns
DIN to SCLK Fall Setup Time t
DS
15 ns
DIN to SCLK Fall Hold Time t
DH
0ns
CS Pulse Width High t
CSW
80 ns