Datasheet

MAX536/MAX537
Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
14 ______________________________________________________________________________________
CS
SCK
SDI
SDO
LDAC*
t
CSO
t
CSS
t
CL
t
CH
t
CP
t
DO1
t
TR
t
CSW
t
CSI
t
LDAC
t
DO2
t
CSH
t
DS
t
DH
t
DV
*USE OF LDAC IS OPTIONAL
Figure 6. Detailed Serial-Interface Timing Diagram
Figure 4. 3-Wire Serial-Interface Timing Diagram (LDAC = GND or V
DD
)
Figure 5. 4-Wire Serial-Interface Timing Diagram for Asynchronous DAC Updating Using LDAC
CS
SCK
SDI
SDO
MSB
MSB FROM
PREVIOUS WRITE
LSB
LSB FROM
PREVIOUS WRITE
D15 D14 D13
D2 D1 D0
..........
Q15 Q0
COMMAND
EXECUTED
..........
..........
...........
9
8
16
1
CS
SCK
SDI
SDO
MSB
MSB FROM
PREVIOUS WRITE
LSB
LSB FROM
PREVIOUS WRITE
D15 D14 D13
D2 D1 D0
..........
Q15 Q0
INPUT REGISTER(S)
UPDATED
..........
..........
..........
98161
DACs
UPDATED
LDAC