Datasheet

MAX532
Dual, Serial-Input,
Voltage-Output, 12-Bit MDAC
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 11.4V to 16.5V, V
SS
= -11.4V to -16.5V, AGNDA = AGNDB = DGND = 0V, VREFA and VREFB = +10V, R
L
= 2kΩ, C
L
= 100pF,
VOUT_ connected to RFB_, T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
PARAMETER CONDITIONS MIN TYP MAX UNITSSYMBOL
VREF = 100mV
p-p
sine wave;
DAC latch loaded with all 1s
1.0 MHz
VREF = 20V
p-p
10kHz sine wave;
DAC latch loaded with all 0s
-77 dB
Full-Power Bandwidth 125 kHz
THDTotal Harmonic Distortion -90 dB
Output Noise Voltage 0.1Hz to 10Hz 2
µV
RMS
Digital Crosstalk DACA code all 1s, DACB code transition from all 0s to all 1s 10 nV-s
Digital Feedthrough
CS = 1; transitions on SCLK, LDAC, DIN
1.1 nV-s
PARAMETER
t
CL
CONDITIONS MIN TYP MAX
SCLK Pulse Width Low
UNITSSYMBOL
f
CLK
t
CH
80 ns
t
DS
50 ns
t
CSS1
CS Rise to SCLK Rise Setup Time
SCLK Clock Frequency
50 ns
t
CSS0
CS Fall to SCLK Rise Setup Time
6.25 MHz
50 ns
t
DH
DIN to SCLK Rise Hold Time 0 ns
SCLK Pulse Width High 80 ns
Multiplying Feedthrough
Error
Unity-Gain Small-Signal
Bandwidth
VREF = 20V
p-p
sine wave;
DAC latch loaded with all 1s
VREF = 6V
RMS
, 1kHz sine wave;
DAC latch loaded with all 1s
Note 1: Static performance tested at V
DD
= +15V, V
SS
= -15V. Performance over supplies guaranteed by PSR test.
Note 2: Guaranteed by design. Not subject to production testing.
Note 3: Open-drain output.
TIMING CHARACTERISTICS
(V
DD
= 11.4V to 16.5V, V
SS
= -11.4V to -16.5V, AGNDA = AGNDB = DGND = 0V) (Notes 4, 5)
t
CSH0
SCLK Fall to CS Fall Hold Time
5 ns
t
CSH1
SCLK Rise to CS Rise Hold Time
80 ns
t
CSW
CS Pulse Width High
120 ns
t
DO
SCLK Fall to DOUT Valid (Note 6)
C
L
= 20pF, R
PULL-UP
= 1kΩ to 5V
0 200 ns
t
DV
CS Fall to DOUT Enable (Note 7)
C
L
= 20pF, R
PULL-UP
= 1kΩ to 5V
100 ns
t
TR
CS Rise to DOUT Disable (Note 7)
C
L
= 20pF, R
PULL-UP
= 1kΩ to 5V
60 ns
t
LDAC
LDAC Pulse Width Low
60 ns
t
LDACS
CS Rise to LDAC Fall Setup Time
100 ns
DIN to SCLK Rise Setup Time
Note 4: All input signals are specified with t
R
= t
F
≤ 5ns. Logic input swing is 0V to 5V.
Note 5: See Figure 1.
Note 6: Timing is for SCLK fall to DOUT fall to 0.8V, or for SCLK fall to DOUT rise to 2.4V. Additional time must be added for any
larger passive RC pull-up delay.
Note 7: DOUT enable: DOUT falls to 4.5V from 5.0V. DOUT disable: DOUT rises to 0.5V from 0V.