Datasheet

MAX5236/MAX5237
Single-Supply 3V/5V, Voltage-Output, Dual,
Precision 10-Bit DACs
_______________________________________________________________________________________ 5
ELECTRICAL CHARACTERISTICS—MAX5236 (continued)
(V
DD
= +2.7V to +3.6V, GND = 0, V
REFA
= V
REFB
= +1.25V, R
L
= 5kΩ, C
L
= 100pF, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Typical values are at T
A
= +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Ti m e Req ui r ed for Outp ut to S ettl e
After Tur ni ng on V
D D
( N ote 7) 60 µs
Time Required for Output to
Settle After Exiting Full Power-
Down
(Note 7)
60
µs
Time Required for Output to
Settle After Exiting DAC Power-
Down
(Note 7) 50 µs
Digital Feedthrough CS = V
DD
, f
SCLK
= 100kHz, V
SCLK
= 3V
P-P
5 nV-s
Major Carry Glitch Energy 115 nV-s
POWER SUPPLIES
Power-Supply Voltage V
DD
2.7 3.6 V
Power-Supply Current I
DD
(Note 8) 325 430 µA
Full power-down mode 0.4 5
One DAC shutdown mode 175 200
Power-Supply Current in Power-
Down and Shutdown Modes
I
SHDN
Both DACs shutdown mode 25 40
µA
TIMING CHARACTERISTICS—MAX5237 (FIGURES 1 AND 2)
(V
DD
= +4.5V to +5.5V, GND = 0, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SCLK Clock Period t
CP
74 ns
SCLK Pulse Width High t
CH
30 ns
SCLK Pulse Width Low t
CL
30 ns
CS Fall to SCLK Rise Setup Time t
CSS
30 ns
SCLK Rise to CS Rise Hold Time t
CSH
0ns
DIN Setup Time t
DS
30 ns
DIN Hold Time t
DH
0ns
SCLK Rise to CS Fall Delay t
CS0
10 ns
CS Rise to SCLK Rise Hold Time t
CS1
30 ns
CS Pulse Width High t
CSW
75 ns
LDAC Pulse Width Low t
LDL
30 ns
CS Rise to LDAC Rise Hold Time t
CSLD
(Note 9) 40 ns