Datasheet
MAX517/MAX518/MAX519
2-Wire Serial 8-Bit DACs with
Rail-to-Rail Outputs
______________________________________________________________________________________ 13
age, both DC and AC signals. The voltage at each REF
input sets the full-scale output voltage for its respective
DAC. The reference voltage must be positive. The
DAC’s input impedance is code dependent, with the
lowest value occurring when the input code is 55 hex or
0101 0101, and the maximum value occurring when the
input code is 00 hex. Since the REF input resistance
(RIN) is code dependent, it must be driven by a circuit
with low output impedance (no more than RIN ÷ 2000)
to maintain output linearity. The REF input capacitance
is also code dependent, with the maximum value
occurring at code FF hex (typically 30pF). The output
voltage for any DAC can be represented by a digitally
programmable voltage source as: V
OUT
= (N x V
REF
) /
256, where N is the numerical value of the DAC’s binary
input code.
Output Buffer Amplifiers
The DAC voltage outputs are internally buffered preci-
sion unity-gain followers that slew up to 1V/µs. The out-
puts can swing from 0V to V
DD
. With a 0V to 4V (or 4V
to 0V) output transition, the amplifier outputs typically
settle to 1/2LSB in 6µs when loaded with 10kΩ in paral-
lel with 100pF. The buffer amplifiers are stable with any
combination of resistive loads ≥2kΩ and capacitive
loads ≤300pF.
The MAX517/MAX518/MAX519 are designed for unipo-
lar-output, single-quadrant multiplication where the out-
put voltages and the reference inputs are positive with
respect to AGND. Table 1 shows the unipolar code.
Table 1. Unipolar Code Table
2R
R
RR
2R 2R 2R 2R 2R
D0 D5 D6 D7
REF_*
GND
SHOWN FOR ALL 1s ON DAC
OUT_
*REF = V
DD
FOR THE MAX518
Figure 15. DAC Simplified Circuit Diagram
( )
SDA
0
START
CONDITION
ADDRESS BYTE ACK
10
1
or
AD3
1
or
AD2
AD1AD0 0 0 0 0 0011
(RST) (PD)
(PD)
EARLY
STOP CONDITION
INTERRUPTED
COMMAND BYTE
MAX517/MAX518/MAX519's
STATE REMAINS UNCHANGED.
( )
SDA
0
START
CONDITION
ADDRESS BYTE ACK
10
1
or
AD3
1
or
AD2
AD1AD000000 000011100RST 1
COMMAND BYTE
(POWER DOWN)
ACK
INTERRUPTED
OUTPUT BYTE
(a)
(b)
MAX517/MAX518/MAX519
POWER DOWN; INPUT LATCH
UNCHANGED IF RST = 0,
DAC OUTPUT(S) RESET IF RST = 1.
EARLY
STOP CONDITION
X X
Figure 14. Early STOP Conditions
DAC CONTENTS
ANALOG OUTPUT
11111111
255
+ V
REF
(
———)
256
10000001
129
+ V
REF
(———)
256
10000000
128 V
REF
+ V
REF
(
———)
= ——
256 2
01111111
127
+ V
REF
(
———)
256
00000001
1
+ V
REF
(
———)
256
00000000 0V