Datasheet
Pin-/Software-Compatible,
16-/12-Bit, Voltage-Output DACs
4 Maxim Integrated
MAX5134–MAX5137
ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= 2.7V to 5.25V, V
DVDD
= 2.7V to 5.25V, V
AVDD
≥ V
DVDD
, V
GND
= 0V, V
REFI
= V
AVDD
- 0.25V, C
OUT
= 200pF, R
OUT
= 10kΩ,
T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
POWER REQUIREMENTS (Note 7)
Analog Supply Voltage Range V
AVDD
2.7 5.25 V
Digital Supply Voltage Range V
DVDD
2.7 V
AVDD
V
I
AVDD
2.5 3.6 mA
Supply Current
(MAX5134/MAX5135)
I
DVDD
No load, all digital inputs at 0 or DVDD
1 10 μA
I
AVDD
1.5 2.3 mA
Supply Current
(MAX5136/MAX5137)
I
DVDD
No load, all digital inputs at 0 or DVDD
1 10 μA
I
AVPD
0.2 2
Power-Down Supply Current
I
DVPD
No load, all digital inputs at 0 or DVDD
0.1 2
μA
TIMING CHARACTERISTICS (Note 8) (Figure 1)
Serial-Clock Frequency f
SCLK
0 30 MHz
SCLK Pulse-Width High t
CH
13 ns
SCLK Pulse-Width Low t
CL
13 ns
CS Fall-to-SCLK Fall Setup Time t
CSS
8 ns
SCLK Fall-to CS-Rise Hold Time t
CSH
5 ns
DIN-to-SCLK Fall Setup Time t
DS
10 ns
DIN-to-SCLK Fall Hold Time t
DH
2 ns
SCLK Fall to READY Transition t
SRL
(Note 9) 30 ns
CS Pulse-Width High t
CSW
33 ns
LDAC Pulse Width t
LDACPWL
33 ns
Note 1: Static accuracy tested without load.
Note 2: Linearity is tested within 20mV of GND and AVDD
,
allowing for gain and offset error.
Note 3: Codes above 2047 are guaranteed to be within ±8 LSB
.
Note 4: Gain and offset tested within 100mV of GND and AVDD
.
Note 5: Guaranteed by design.
Note 6: Device draws current in excess of the specified supply current when a digital input is driven with a voltage of VI < V
DVDD
- 0.6V
or VI > 0.5V. At VI = 2.2V with V
DVDD
= 5.25V, this current can be as high as 2mA. The SPI inputs are CMOS-input level com-
patible. The 30MHz clock frequency cannot be guaranteed for a minimum signal swing.
Note 7: Excess current from AVDD is 10mA when powered without DVDD. Excess current from DVDD is 1mA when powered without
AVDD.
Note 8: All timing specifications are with respect to the digital input and output thresholds.
Note 9: Maximum daisy-chain clock frequency is limited to 25MHz.
C7
C6
C5 D2
D1
D0
X
COMMAND EXECUTED ON
24TH FALLING EDGE OF SCLK
CS
SCLK
DIN
X = DON'T CARE.
t
CH
t
CL
t
CSS
t
DH
t
CSH
t
DS
t
SRL
READY
X
t
CSW
D3
Figure 1. Serial-Interface Timing Diagram