Datasheet

input latches. To avoid output glitches in the MAX5102,
ensure that data is valid before WR goes low. When the
device powers up (i.e., V
DD
ramps up), all latches are
internally preset with code 00 hex.
Applications Information
External Reference
The reference source resistance must be considerably
less than the reference input resistance. To keep within
1LSB error in an 8-bit system, R
S
must be less than
R
REF
/256. Hence, maintain a value of R
S
< 1kΩ to
ensure 8-bit accuracy. If V
REF
is DC only, bypass REF
to GND with a 0.1µF capacitor. Values greater than this
improve noise rejection.
Power Sequencing
The voltage applied to REF should not exceed V
DD
at
any time. If proper power sequencing is not possible,
connect an external Schottky diode between REF and
V
DD
to ensure compliance with the absolute maximum
ratings. Do not apply signals to the digital inputs before
the device is fully powered up.
Power-Supply Bypassing and
Ground Management
Digital or AC transient signals on GND can create noise
at the analog output. Return GND to the highest-quality
ground available. Bypass V
DD
with a 0.1µF capacitor,
located as close to V
DD
and GND as possible.
Careful PC board ground layout minimizes crosstalk
between the DAC outputs and digital inputs.
Chip Information
TRANSISTOR COUNT: 6848
MAX5102
+2.7V to +5.5V, Low-Power, Dual, Parallel
8-Bit DAC with Rail-to-Rail Voltage Outputs
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