Datasheet

MAX509/MAX510
Quad, Serial 8-Bit DACs
with Rail-to-Rail Outputs
10 ______________________________________________________________________________________
• • •
• • •
• • •
• • •
• • •
t
LDW
SCLK
DIN
DOUT
LDAC
CS
t
DO
t
DH
t
DS
t
CSH0
t
CSS
t
CH
t
CL
t
CSH1
t
CSH2
t
CLL
NOTE: TIMING SPECIFICATION t
CLL
IS RECOMMENDED TO MINIMIZE OUTPUT GLITCH, BUT IS NOT MANDATORY.
Figure 2. Detailed Serial Interface Timing (Mode 0 Shown)
Table 1. Serial-Interface Programming Commands
Mode 0, DOUT clocked out on falling edge of SCLK.
All DACs updated from input registers.
Mode 1, DOUT clocked out on rising edge of SCLK
(default). All DACs updated from respective input
registers.
“LDAC” Command, all DACs updated from respective
input registers.
12-Bit Serial Word
0
0
1
1
0
0
1
1
C0
0
0
0
0
0
1
1
1
1
1
1
1
1
C1
1
1
1
0
0
1
1
1
1
0
0
0
0
A0
0
1
X
1
0
0
1
0
1
0
1
0
1
FunctionLDAC
D7 . . . . . . . . D0
A1
XX X X X X X X X1
XX X X X X X X X1
XX X X X X X X X0
No Operation (NOP), shifts data in shift register.XX X X X X X X X X
Update all DACs from shift register.X8-Bit DAC DataX
Load input and DAC register A.
Load input and DAC register B.
Load input and DAC register C.
Load input and DAC register D.
1
1
1
1
8-Bit DAC Data
8-Bit DAC Data
8-Bit DAC Data
8-Bit DAC Data
Load DAC A input register, DAC output unchanged.
Load DAC B input register, DAC output unchanged.
Load DAC C input register, DAC output unchanged.
Load DAC D input register, DAC output unchanged.
1
1
1
1
8-Bit DAC Data
8-Bit DAC Data
8-Bit DAC Data
8-Bit DAC Data