Datasheet

MAX4996/MAX4996L
Triple DPDT, Low-Capacitance Data Switches
8 _______________________________________________________________________________________
V
IN+
V
IN-
CB
V
OUT+
V
OUT-
V
IN+
V
IN-
V
OUT+
V
OUT-
NC OR
NO_
NC OR
NO_
COM_
COM_
0V
V
CC
V
CC
V
CC
V
CC
0V
0V
0V
t
PLHX
t
PHLX
t
SKEW
= |t
PLHX
- t
PLHY
| OR |t
PHLX
- t
PHLY
|
50%
50%
50%
50%
R
L
R
L
50%
50%
50%
50%
t
PHLY
t
PLHY
R
S
R
S
V
IL
TO V
IH
MAX4996/
MAX4996L
Figure 3. Input/Output Skew Timing Diagram
Timing Circuits/Timing Diagrams (continued)