Datasheet

MAX4996/MAX4996L
Triple DPDT, Low-Capacitance Data Switches
_______________________________________________________________________________________ 7
Timing Circuits/Timing Diagrams
t
r
< 5ns
t
f
< 5ns
50%
0V
LOGIC
INPUT
R
L
COM_
CB_
C
L
INCLUDES FIXTURE AND STRAY CAPACITANCE.
V
OUT
= V
IN (
R
L
)
R
L
+ R
ON
V
IN
V
CC
t
OFF
0V
NO_
OR NC_
0.9 x V
0UT
0.9 x V
OUT
t
ON
V
OUT
SWITCH
OUTPUT
LOGIC
INPUT
C
L
V
OUT
MAX4996
MAX4996L
50%
Figure 1. Switching Time
50%
V
CC
0V
LOGIC
INPUT
V
OUT
0.9 x V
OUT
t
BBM
LOGIC
INPUT
R
L
C
L
INCLUDES FIXTURE AND STRAY CAPACITANCE.
NO_
CB_
NC_
V
OUT
C
L
V
IN
COM_
MAX4996
MAX4996L
Figure 2. Break-Before-Make Interval