Datasheet

MAX4551/MAX4552/MAX4553
±15kV ESD-Protected, Quad,
Low-Voltage, SPST Analog Switches
10 ______________________________________________________________________________________
V
GEN
GND
NC or
NO
C
L
V
OUT
-5V
V-
V+
V
OUT
IN
OFF
ON
OFF
∆V
OUT
Q = (∆V
OUT
)(C
L
)
COM
IN DEPENDS ON SWITCH CONFIGURATION;
INPUT POLARITY DETERMINED BY SENSE OF SWITCH.
OFF
ON
OFF
IN
V
IN
= +3V
+5V
R
GEN
IN
MAX4551
MAX4552
MAX4553
Figure 3. Charge Injection
t
r
< 20ns
t
f
< 20ns
50%
0V
LOGIC
INPUT
V-
-5V
R
L
300Ω
NO
or NC
GND
C
L
INCLUDES FIXTURE AND STRAY CAPACITANCE.
V
OUT
= V
COM (
R
L
)
R
L
+ R
ON
SWITCH
INPUT
IN, EN
+3V
t
OFF
0V
COM
SWITCH
OUTPUT
0.9 · V
0UT
0.9 · V
OUT
t
ON
V
OUT
SWITCH
OUTPUT
LOGIC
INPUT
LOGIC INPUT WAVEFORMS INVERTED FOR EN AND SWITCHES
THAT HAVE THE OPPOSITE LOGIC SENSE.
C
L
35pF
+5V
V+
V
OUT
V
COM
0V
MAX4551
MAX4552
MAX4553
50%
0.9 · V
0UT1
+3V
0V
0V
LOGIC
INPUT
SWITCH
OUTPUT 2
(V
OUT2
)
0V
0.9 · V
OUT2
t
D
t
D
LOGIC
INPUT
V-
-5V
R
L2
GND
C
L
INCLUDES FIXTURE AND STRAY CAPACITANCE.
COM2
IN1, 2
COM1
V
OUT2
V+
+5V
C
L2
V
COM1
R
L1
V
OUT1
C
L1
R
L
= 300Ω
C
L
= 35pF
NO
NC
SWITCH
OUTPUT 1
(V
OUT1
)
MAX4553
V
COM2
Figure 1. Switching Time
Figure 2. Break-Before-Make Interval (MAX4553 only)
Test Circuits/Timing Diagrams