Datasheet

__________ Applications Information
Transceivers on the Bus
The MAX3471 is optimized for the unterminated bus
normally used in slow, low-power systems. With
a +2.5V supply, the part is guaranteed to drive up to
eight standard loads (for example, 64 other MAX3471s or
56 MAX3471s plus one standard load). Drive capability
increases significantly with supply. For example, with
a +5V supply, the MAX3471 typically meets the RS-485
driver output specifications (1.5V with 54Ω differential ter-
mination). See the Typical Operating Characteristics .
Reduced EMI and Reflections
The MAX3471 is slew-rate limited, minimizing EMI and
reducing reflections caused by improperly terminated
cables. In general, the rise time of a transmitter directly
relates to the length of an unterminated stub, which can
be driven with only minor waveform reflections. The fol-
lowing equation expresses this relationship conserva-
tively:
Length = t
RISE
/ (10 x 1.5ns/foot)
where t
RISE
is the transmitter’s rise time.
For example, the MAX3471’s rise time is typically 1.3µs,
which results in excellent waveforms with a stub length
up to 82 feet. In general, systems operate well with
longer unterminated stubs, even with severe reflec-
tions, if the waveform settles out before the UART sam-
ples them.
Driver Output Protection
Excessive output current and power dissipation caused
by faults or bus contention are prevented by foldback
current limiting. A foldback current limit on the output
stage provides immediate protection against short cir-
cuits over the whole common-mode voltage range (see
Typical Operating Characteristics ).
MAX3471
1.6µA, RS-485/RS-422, Half-Duplex,
Differential Transceiver for Battery-Powered Systems
_______________________________________________________________________________________ 7
Table 1. Transmitting Table 2. Receiving
INPUTS
RREE
DE DI A
X 1 1 1
X 1 0 0
0 0 X Z
D
1 0 X Z
D
B
0
1
Z
D
Z
D
OUTPUTS
1
0 0
0
INPUTS
RREE
DE RO
0 0 1
0
0 0 1
Z
A-B
≥ -0.05V
≤ -0.45V
Open/Shorted
X
OUTPUT
X = Don’t care
Z = Receiver output high impedance
Figure 1. Driver DC Test Load
S2
1k
C
L
RECEIVER
OUTPUT
V
CC
S1
TEST
POINT
Figure 2. Receiver Enable/Disable Timing Test Load
Z
D
= Driver output disabled
A
R
R
B
V
OD
V
OC
DE
DI
A
B
DRIVER
V
O
V
CC
R
DIFF
C
L1
C
L2
Figure 3. Driver Test Circuit