Datasheet

Dual Serial UART with 128-Word FIFOs
MAX3109
23Maxim Integrated
Both portions of the delay are dependent on the UART’s
clock. When the fractional divider is not used, the intrinsic
trigger delay, t
TRIG
, is bounded by the following limits:
TRIG
56
t
UARTCLK UARTCLK
≤≤
where UARTCLK is the baud-rate divider output. The
reference point is the time when the trigger command is
received by the MAX3109. This occurs on the final (i.e.,
the 16th) SPI clock’s low-to-high transition (Figure 12).
In I
2
C mode, this occurs on the final (i.e., the 8th) SCL
low-to-high transition.
When the fractional baud-rate generator is used, the
random portion is larger than one UART clock period.
Synchronization Accuracy
When synchronizing multiple UART transmitters, the out-
put skew of the TX_ transmitter outputs is based on the
triggering delays of each UART (Figure 13). This skew
has a baud rate dependent component, similar to the
Figure 12. Single Transmitter Trigger Accuracy
Figure 13. Multiple Transmitter Synchronization Accuracy
UNCERTAINTY
INTERVAL
t
TRIG_MIN
t
TRIG_MAX
TX_
SCLK
t
TX1_MAX
t
TRIGSKEW
t
TX1_MIN
t
TX0_MAX
t
TX0_MIN
TX0
TX1
SCLK