Datasheet

SPI/I

C UART with 128-Word FIFOs

MAX3107

24 Maxim Integrated

Bits 7–0: TData[7:0]

The THR is the register that the host controller writes data to for subsequent UART transmission. This data is deposited

in the transmit FIFO. THR[0] is the LSB. It is the first data bit of the serial-data word that the transmitter sends out, right

after the START bit.

The IRQEn is used to enable the IRQ physical interrupt. Any of the eight ISR interrupt sources can be enabled to gener-

ate an IRQ. The IRQEn bits only influence the IRQ output and do not have any effect on the ISR contents or behavior.

Every one of the IRQEn bits operates on an ISR bit.

Bit 7: CTSIEn

The CTSIEn bit enables IRQ interrupt generation when the CTSInt interrupt bit is set in the ISR. Set CTSIEn bit low to

disable IRQ generation from CTSInt.

Bit 6: RxEmtyIEn

The RxEmtyIEn bit enables IRQ interrupt generation when the RxEmtyInt interrupt bit is set in the ISR. Set RxEmtyIEn

bit low to disable IRQ generation from RxEmtyInt.

Bit 5: TxEmtyIEn

The TxEmtyIEn bit enables IRQ interrupt generation when the TxEmptyInt interrupt bit is set in the ISR. Set TxEmtyIEn

bit low to disable IRQ generation from TxEmptyInt.

Bit 4: TxTrgIEn

The TxTrgIEn bit enables IRQ interrupt generation when the TFifoTrigInt interrupt bit is set in the ISR. Set TxTrgIEn bit

low to disable IRQ generation from TFifoTrigInt.

Bit 3: RxTrgIEn

The RxTrgIEn bit enables IRQ interrupt generation when the RFifoTrigInt interrupt bit is set in the ISR. Set RxTrgIEn bit

low to disable IRQ generation from RFifoTrigInt.

Bit 2: STSIEn

The STSIEn bit enables IRQ interrupt generation when the STSInt interrupt bit is set in the ISR. Set STSIEn bit low to

disable IRQ generation from STSInt.

Bit 1: SpclChrlEn

The SpclChrIEn bit enables IRQ interrupt generation when the SpCharInt interrupt bit is set in the ISR. Set SpclChrIEn

bit low to disable IRQ generation from SpCharInt.

THR—Transmit Hold Register

IRQEn—IRQ Enable Register

ADDRESS: 0x00

MODE: W

BIT 7 6 5 4 3 2 1 0

NAME

TData7 TData6 TData5 TData4 TData3 TData2 TData1 TData0

ADDRESS: 0x01

MODE: R/W

BIT 7 6 5 4 3 2 1 0

NAME

CTSIEn RxEmtyIEn TxEmtyIEn TxTrgIEn RxTrgIEn STSIEn SpclChrIEn LSRErrIEn

RESET

0 0 0 0 0 0 0 0