Datasheet

MAX197
How to Start a Conversion
Conversions are initiated with a write operation, which
selects the mux channel and configures the MAX197 for
either unipolar or bipolar input range. A write pulse (WR
+ CS) can either start an acquisition interval or initiate a
combined acquisition plus conversion. The sampling
interval occurs at the end of the acquisition interval.
The ACQMOD bit in the input control byte offers two
options for acquiring the signal: internal or external.
The conversion period lasts for 12 clock cycles in either
internal or external clock or acquisition mode.
Writing a new control byte during conversion cycle will
abort conversion and start a new acquisition interval.
Internal Acquisition
Select internal acquisition by writing the control byte
with the ACQMOD bit cleared (ACQMOD = 0). This
causes the write pulse to initiate an acquisition interval
whose duration is internally timed. Conversion starts
when this six-clock-cycle acquisition interval (3µs with
f
CLK
= 2MHz) ends. See Figure 5.
External Acquisition
Use the external acquisition timing mode for precise con-
trol of the sampling aperture and/or independent control
of acquisition and conversion times. The user controls
acquisition and start-of-conversion with two separate
write pulses. The first pulse, written with ACQMOD = 1,
starts an acquisition interval of indeterminate length. The
second write pulse, written with ACQMOD = 0, termi-
nates acquisition and starts conversion on WR’s rising
edge (Figure 6). However, if the second control byte
contains ACQMOD = 1, an indefinite acquisition interval
is restarted.
The address bits for the input mux must have the same
values on the first and second write pulses. Power-
down mode bits (PD0, PD1) can assume new values on
the second write pulse (see Power-Down Mode).
Multi-Range (±10V, ±5V, +10V, +5V),
Single +5V, 12-Bit DAS with 8+4 Bus Interface
10 ______________________________________________________________________________________
t
CS
t
CSWS
t
WR
t
ACQI
t
CONV
t
DH
t
DS
t
INT1
t
D0
t
D01
t
TR
HGH-ZHGH-Z
t
CSRS
t
CSRH
CS
WR
D7–D0
INT
RD
HBEN
DOUT
ACQMOD ="0"
HIGH / LOW
BYTE VALID
HIGH / LOW
BYTE VALID
CONTROL
BYTE
t
CSWH
Figure 5. Conversion Timing Using Internal Acquisition Mode
Table 6. Data-Bus Output
PIN HBEN = LOW HBEN = HIGH
D0 B0 (LSB) B8
D1 B1 B9
D2 B2 B10
D3 B3 B11 (MSB)
D4 B4 B11 (BIP = 1) / 0 (BIP = 0)
D5 B5 B11 (BIP = 1) / 0 (BIP = 0)
D6 B6 B11 (BIP = 1) / 0 (BIP = 0)
D7 B7 B11 (BIP = 1) / 0 (BIP = 0)