Datasheet

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MAX19706

10-Bit, 22Msps, Ultra-Low-Power

Analog Front-End

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12-Bit Auxiliary Control DACs

The MAX19706 includes three 12-bit aux-DACs (DAC1,

DAC2, DAC3) with 1µs settling time for controlling VGA,

AGC, and AFC functions. The aux-DAC output range is

0.1V to 2.56V. During power-up, the VGA and AGC out-

puts (DAC2 and DAC3) are at zero. The AFC DAC

(DAC1) is at 1.1V during power-up. The aux-DACs can

be independently controlled through the SPI bus,

except during SHDN mode where the aux-DACs are

turned off completely and the output voltage is set to

zero. In STBY and IDLE modes, the aux-DACs maintain

the last value. On wakeup from SHDN, the aux-DACs

resume the last values.

Loading on the aux-DAC outputs should be carefully

observed to achieve specified settling time and stabili-

ty. The capacitive load must be kept to a maximum of

5pF including package and trace capacitance. The

resistive load must be greater than 200kΩ. If capacitive

loading exceeds 5pF, then add a 10kΩ resistor in

series with the output. Adding the series resistor helps

drive larger load capacitance (< 15pF) at the expense

of slower settling time.

10-Bit, 333ksps Auxiliary ADC

The MAX19706 integrates a 10-bit, 333ksps aux-ADC

with an input 4:1 multiplexer. In the aux-ADC mode reg-

ister, setting bit AD0 begins a conversion with the auxil-

iary ADC. Bit AD0 automatically clears when the

conversion is complete. Setting or clearing AD0 during

a conversion has no effect (see Table 11). Bit AD1

determines the internal reference of the auxiliary ADC

(see Table 12). Bits AD2 and AD3 determine the auxil-

iary ADC input source (see Table 13). Bits AD4, AD5,

and AD6 select the number of averages taken when a

single start-convert command is given. The conversion

time increases as the number of averages increases

(see Table 14). The conversion clock can be divided

down from the system clock by properly setting bits

AD7, AD8, and AD9 (see Table 15). The aux-ADC out-

put data can be written out of DOUT by setting bit

AD10 high (see Table 16).

The aux-ADC features a 4:1 input multiplexer to allow

measurements on four input sources. The input sources

are selected by AD3 and AD2 (see Table 13). Two of

the multiplexer inputs (ADC1 and ADC2) can be con-

nected to external sources such as an RF power detec-

tor like the MAX2208 or temperature sensor like the

MAX6613. The other two multiplexer inputs are internal

connections to V

and OV

that monitor the power-

supply voltages. The internal V

and OV

connec-

tions are made through integrated resistor-dividers that

yield V

/ 2 and OV

/ 2 measurement results. The

aux-ADC voltage reference can be selected between

an internal 2.048V bandgap reference or V

(see

Table 12). The V

reference selection is provided to

allow measurement of an external voltage source with a

full-scale range extending beyond the 2.048V level. The

input source voltage range cannot extend above V

Table 11. Auxiliary ADC Convert

Table 12. Auxiliary ADC Reference

Table 13. Auxiliary ADC Input Source

AD0 SELECTION

0 Aux-ADC Idle (Default)

1 Aux-ADC Start-Convert

AD1 SELECTION

0 Internal 2.048V Reference (Default)

1 Internal V

Reference

AD3 AD2 AUX-ADC INPUT SOURCE

0 0 ADC1 (Default)

0 1 ADC2

10 V

/ 2

11 OV

/ 2