Datasheet

MAX19507
Dual-Channel, 8-Bit, 130Msps ADC
_______________________________________________________________________________________ 5
ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= V
OVDD
= 1.8V, internal reference, differential clock, V
CLK
= 1.5V
P-P
, f
CLK
= 130MHz, A
IN
= -0.5dBFS, data output termina-
tion = 50Ω, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at T
A
= +25°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
CLOCK INPUT (SYNC)
Allowable Logic Swing 0 - V
AVDD
V
Sync Clock Input High Threshold 1.5 V
Sync Clock Input Low Threshold 0.3 V
V
SYNC
= V
AVDD
= 1.8V or 3.3V +0.5
Input Leakage
V
SYNC
= 0V -0.5
µA
Input Capacitance 4.5 pF
DIGITAL INPUTS (SHDN, SPEN)
Allowable Logic Swing 0 - V
AVDD
V
Input High Threshold 1.5 V
Input Low Threshold 0.3 V
V
SHDN
/V
SPEN
= V
AVDD
= 1.8V or 3.3V +0.5
Input Leakage
V
SHDN
/V
SPEN
= 0V -0.5
µA
Input Capacitance C
DIN
3pF
SERIAL-PORT INPUTS (SCLK, SDIN, CS, where SPEN = 0V)—SERIAL-PORT CONTROL MODE
Allowable Logic Swing 0 - V
AVDD
V
Input High Threshold 1.5 V
Input Low Threshold 0.3 V
V
SCLK
/V
SDIN
/V
CS
= V
AVDD
= 1.8V or 3.3V +0.5
Input Leakage
V
SCLK
/V
SDIN
/V
CS
= 0V -0.5
µA
Input Capacitance C
DIN
3pF
SERIAL-PORT INPUTS (SCLK, SDIN, CS, where SPEN = V
AVDD
)—PARALLEL CONTROL MODE (Figure 5)
V
SCLK
/V
SDIN
/V
CS
= V
AVDD
= 1.8V 7 12 17
Input Pullup Current
V
SCLK
/V
SDIN
/V
CS
= V
AVDD
= 3.3V 16 21 26
µA
V
SCLK
/V
SDIN
/V
CS
= 0V, V
AVDD
= 1.8V -65 -50 -35
Input Pulldown Current
V
SCLK
/V
SDIN
/V
CS
= 0V, V
AVDD
= 3.3V -105 -90 -75
µA
V
AVDD
= 1.8V 1.35 1.45 1.55
Open-Circuit Voltage V
OC
V
AVDD
= 3.3V 2.58 2.68 2.78
V
DIGITAL OUTPUTS (CMOS MODE 75Ω, D0–D7 (A and B Channel), DCLKA, DCLKB, DORA, DORB)
Output-Voltage Low V
OL
I
SINK
= 200µA 0.2 V
Output-Voltage High V
OH
I
SOURCE
= 200µA
V
OVDD
- 0.2
V
V
OVDD
applied +0.5
Three-State Leakage Current I
LEAK
GND applied -0.5
µA