Datasheet

MAX19507

Dual-Channel, 8-Bit, 130Msps ADC

20 ______________________________________________________________________________________

Data/DCLK Timing (03h)

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

DA_BYPASS DLY_HALF_T DCLKTIME_2 DCLKTIME_1 DCLKTIME_0 DTIME_2 DTIME_1 DTIME_0

Bit 7 DA_BYPASS: Data aligner bypass

0 = Nominal (default)

1 = Bypasses data aligner delay line to minimize output data latency with respect to the input clock.

Rising clock to data transition is approximately 6ns with DTIME = 000b settings

Bit 6 DLY_HALF_T: Data and DCLK delayed by T/2

0 = Normal, no delay

1 = Delays data and DCLK outputs by T/2 (default)

Disabled in MUX data bus mode

Bit 5, 4, 3 DCLKTIME_2, DCLKTIME_1, DCLKTIME_0: DCLK timing adjust (controls both channels)

000 = Nominal

001 = +T/16

010 = +2T/16

011 = +3T/16

100 = Reserved, do not use

101 = -1T/16 (default)

110 = -2T/16

111 = -3T/16

Bit 2, 1, 0 DTIME_2, DTIME_1, DTIME_0: Data timing adjust (controls both channels)