Datasheet

MAX19507
Dual-Channel, 8-Bit, 130Msps ADC
14 ______________________________________________________________________________________
T/H
INA+
CMA
REFIO
CMB
INA-
OUTPUT
DRIVERS
DATA
AND
OUTPUT
FORMAT
PIPELINE
ADC
PIPELINE
ADC
CLOCK
CLOCK
DIGITAL
ERROR
CORRECTION
INTERNAL
REFERENCE
GENERATOR
REFERENCE
AND BIAS
SYSTEM
DIGITAL
ERROR
CORRECTION
DUTY-
CYCLE
EQUALIZER
CLOCK
DIVIDER
D0A–D7A
DCLKB
SHDN
GND
DORB
D0B–D7B
OVDD
(1.8V TO 3.3V)
AVDD
(1.8V OR
2.5V TO 3.3V)
DCLKA
DORA
T/H
INB+
INB-
CLK+
CLK-
SYNC
CS
SCLK
SDIN
SERIAL PORT
AND
CONTROL REGISTERS
INTERNAL CONTROL
1.8V INTERNAL
REGULATOR
AND
POWER CONTROL
SPEN
MAX19507
MAX19507
C
PAR
0.7pF
INA+
*V
COM
*V
COM
PROGRAMMABLE FROM 0.45V TO 1.35V. SEE COMMON-MODE REGISTER (08h)
AVDD
CMA
2kΩ
2kΩ
C
SAMPLE
1.2pF
C
SAMPLE
1.2pF
C
PAR
0.7pF
INA-
AVDD
SAMPLING CLOCK
R
SWITCH
120Ω
R
SWITCH
120Ω
Figure 2. Functional Diagram
Figure 3. Internal Track-and-Hold (T/H) Circuit