Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal TQFN 48

General Description

The MAX19507 dual-channel, analog-to-digital converter

(ADC) provides 8-bit resolution and a maximum sample

rate of 130Msps.

The MAX19507 analog input accepts a wide 0.4V to

1.4V input common-mode voltage range, allowing DC-

coupled inputs for a wide range of RF, IF, and base-

band front-end components. The MAX19507 provides

excellent dynamic performance from baseband to high

input frequencies beyond 400MHz, making the device

ideal for zero-intermediate frequency (ZIF) and high-

intermediate frequency (IF) sampling applications. The

typical signal-to-noise ratio (SNR) performance is

49.8dBFS and typical spurious-free dynamic range

(SFDR) is 69dBc at f

= 70MHz and f

CLK

= 130MHz.

The MAX19507 operates from a 1.8V supply.

Additionally, an integrated, self-sensing voltage regula-

tor allows operation from a 2.5V to 3.3V supply (AVDD).

The digital output drivers operate on an independent

supply voltage (OVDD) over the 1.8V to 3.5V range.

The analog power consumption is only 74mW per chan-

nel at V

AVDD

= 1.8V. In addition to low operating

power, the MAX19507 consumes only 1mW in power-

down mode and 21mW in standby mode.

Various adjustments and feature selections are avail-

able through programmable registers that are

accessed through the 3-wire serial-port interface.

Alternatively, the serial-port interface can be disabled,

with the three inputs available to select output mode,

data format, and clock-divider mode. Data outputs are

available through a dual parallel CMOS-compatible out-

put data bus that can also be configured as a single

multiplexed parallel CMOS bus.

The MAX19507 is available in a small 7mm x 7mm, 48-

pin thin QFN package and is specified over the -40°C

to +85°C extended temperature range.

Refer to the MAX19515, MAX19516, and MAX19517

data sheets for pin- and feature-compatible 10-bit,

65Msps, 100Msps, and 130Msps versions, respectively.

Refer to the MAX19505 and MAX19506 data sheets for

pin- and feature-compatible 8-bit, 65Msps and 100Msps

versions, respectively.

Applications

IF and Baseband Communications, Including

Cellular Base Stations and Point-to-Point

Microwave Receivers

Ultrasound and Medical Imaging

Portable Instrumentation and Low-Power Data

Acquisition

Digital Set-Top Boxes

Features

o Very-Low-Power Operation (74mW/Channel at

130Msps)

o 1.8V or 2.5V to 3.3V Analog Supply

o Excellent Dynamic Performance

49.8dBFS SNR at 70MHz

69dBc SFDR at 70MHz

o User-Programmable Adjustments and Feature

Selection through an SPI™ Interface

o Selectable Data Bus (Dual CMOS or Single

Multiplexed CMOS)

o DCLK Output and Programmable Data Output

Timing Simplifies High-Speed Digital Interface

o Very Wide Input Common-Mode Voltage Range

(0.4V to 1.4V)

o Very High Analog Input Bandwidth (> 850MHz)

o Single-Ended or Differential Analog Inputs

o Single-Ended or Differential Clock Input

o Divide-by-One (DIV1), Divide-by-Two (DIV2), and

Divide-by-Four (DIV4) Clock Modes

o Two’s Complement, Gray Code, and Offset Binary

Output Data Format

o Out-of-Range Indicator (DOR)

o CMOS Output Internal Termination Options

(Programmable)

o Reversible Bit Order (Programmable)

o Data Output Test Patterns

o Small 7mm x 7mm, 48-Pin Thin QFN Package with

Exposed Pad

MAX19507

Dual-Channel, 8-Bit, 130Msps ADC

________________________________________________________________

Maxim Integrated Products

Ordering Information

19-4311; Rev 1; 9/10

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,

or visit Maxim’s website at www.maxim-ic.com.

EVALUATION KIT

AVAILABLE

PART TEMP RANGE PIN-PACKAGE

MAX19507ETM+ -40°C to +85°C 48 TQFN-EP*

Denotes a lead(Pb)-free/RoHS-compliant package.

EP = Exposed pad.

Pin Configuration appears at end of data sheet.

SPI is a trademark of Motorola, Inc.

Summary of content (35 pages)

PAGE 1
9-4311; Rev 1; 9/10 KIT ATION EVALU E L B A IL AVA Dual-Channel, 8-Bit, 130Msps ADC The MAX19507 dual-channel, analog-to-digital converter (ADC) provides 8-bit resolution and a maximum sample rate of 130Msps. The MAX19507 analog input accepts a wide 0.4V to 1.4V input common-mode voltage range, allowing DCcoupled inputs for a wide range of RF, IF, and baseband front-end components.
PAGE 2
MAX19507 Dual-Channel, 8-Bit, 130Msps ADC ABSOLUTE MAXIMUM RATINGS OVDD, AVDD to GND............................................-0.3V to +3.6V CMA, CMB, REFIO, INA+, INA-, INB+, INB- to GND ......................................................-0.3V to +2.1V CLK+, CLK-, SYNC, SPEN, CS, SCLK, SDIN to GND ..........-0.3V to the lower of (VAVDD + 0.3V) and +3.6V DCLKA, DCLKB, D7A–D0A, D7B–D0B, DORA, DORB to GND..........-0.3V to the lower of (VOVDD + 0.3V) and +3.
PAGE 3
Dual-Channel, 8-Bit, 130Msps ADC (VAVDD = VOVDD = 1.8V, internal reference, differential clock, VCLK = 1.5VP-P, fCLK = 130MHz, AIN = -0.5dBFS, data output termination = 50Ω, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DYNAMIC PERFORMANCE Small-Signal Noise Floor Signal-to-Noise Ratio SSNF SNR fIN = 70MHz, < -35dBFS -49.8 fIN = 3MHz 49.8 fIN = 70MHz 49.
PAGE 4
MAX19507 Dual-Channel, 8-Bit, 130Msps ADC ELECTRICAL CHARACTERISTICS (continued) (VAVDD = VOVDD = 1.8V, internal reference, differential clock, VCLK = 1.5VP-P, fCLK = 130MHz, AIN = -0.5dBFS, data output termination = 50Ω, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS INTERCHANNEL CHARACTERISTICS Crosstalk Gain Match fINA or fINB = 70MHz at -1dBFS 95 fINA or fINB = 175MHz at -1dBFS 85 dBc fIN = 70MHz ±0.
PAGE 5
Dual-Channel, 8-Bit, 130Msps ADC (VAVDD = VOVDD = 1.8V, internal reference, differential clock, VCLK = 1.5VP-P, fCLK = 130MHz, AIN = -0.5dBFS, data output termination = 50Ω, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS CLOCK INPUT (SYNC) Allowable Logic Swing 0 - VAVDD Sync Clock Input High Threshold V 1.5 V Sync Clock Input Low Threshold 0.3 VSYNC = VAVDD = 1.8V or 3.3V Input Leakage VSYNC = 0V +0.
PAGE 6
MAX19507 Dual-Channel, 8-Bit, 130Msps ADC ELECTRICAL CHARACTERISTICS (continued) (VAVDD = VOVDD = 1.8V, internal reference, differential clock, VCLK = 1.5VP-P, fCLK = 130MHz, AIN = -0.5dBFS, data output termination = 50Ω, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS POWER-MANAGEMENT CHARACTERISTICS Wake-Up Time from Shutdown tWAKE Internal reference, CREFIO = 0.
PAGE 7
Dual-Channel, 8-Bit, 130Msps ADC (VAVDD = VOVDD = 1.8V, internal reference, differential clock, VCLK = 1.5VP-P, fCLK = 130MHz, AIN = -0.5dBFS, data output termination = 50Ω, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.
PAGE 8
Typical Operating Characteristics (VAVDD = VOVDD = 1.8V, internal reference, differential clock, VCLK = 1.5VP-P, fCLK = 130MHz, AIN = -0.5dBFS, data output termination = 50Ω, TA = +25°C, unless otherwise noted.) -60 -40 -60 -40 -60 -70 -80 -80 -80 -90 -90 0 60 -50 -60 -70 -30 -40 -50 -60 -70 -20 -30 -40 -50 -60 -70 -80 -80 -90 -90 -90 -100 -100 20 40 FREQUENCY (MHz) 0 60 INTEGRAL NONLINEARITY vs. DIGITAL OUTPUT CODE 0 0.10 0.08 0.06 0.04 0.02 0.02 DNL (LSB) 0.04 0 -0.02 0 -0.
PAGE 9
Dual-Channel, 8-Bit, 130Msps ADC 65 -THD SINAD SNR 50 60 SNR -THD 40 -60 60 SFDR2 60 SINAD SNR -50 -40 45 -30 -20 -10 90 0 100 110 120 130 ANALOG INPUT AMPLITUDE (dBFS) SAMPLING FREQUENCY (Msps) PERFORMANCE vs. COMMON-MODE VOLTAGE PERFORMANCE vs. ANALOG SUPPLY VOLTAGE PERFORMANCE vs. ANALOG SUPPLY VOLTAGE 70 SFDR2 60 SINAD SNR 75 70 SFDR2 65 60 55 50 SINAD SNR SFDR1 80 0.75 0.95 1.15 75 70 SFDR2 65 60 SINAD SNR 50 45 45 1.65 1.35 -THD 55 50 0.55 1.75 1.
PAGE 10
Typical Operating Characteristics (continued) (VAVDD = VOVDD = 1.8V, internal reference, differential clock, VCLK = 1.5VP-P, fCLK = 130MHz, AIN = -0.5dBFS, data output termination = 50Ω, TA = +25°C, unless otherwise noted.) 86 84 82 80 VOVDD = 1.8V 20 15 10 5 50 2.5 2.7 2.9 3.1 3.3 35 30 25 20 15 10 0 90 3.5 100 110 90 130 120 DIGITAL SUPPLY CURRENT vs. TEMPERATURE DIGITAL SUPPLY CURRENT vs. SUPPLY VOLTAGE DIGITAL SUPPLY CURRENT vs. SUPPLY VOLTAGE 30 VOVDD = 1.
PAGE 11
Dual-Channel, 8-Bit, 130Msps ADC REFERENCE VOLTAGE (V) 0 -0.1 -0.2 -0.3 -0.4 -0.5 1.2495 1.2474 1.2453 1.6 1.4 1.2 VCM = 1.35V VCM = 1.2V VCM = 1.05V 1.0 VCM = 0.9V 0.8 VCM = 0.75V 0.6 MAX19507 toc30 0.1 MAX19507 toc29 1.2516 MAX19507 toc28 0.2 VCM = 0.6V VCM = 0.45V 0.4 0.2 -0.6 -0.7 0 1.2432 10 60 -40 TEMPERATURE (°C) 10 60 -40 110 100 INPUT CURRENT (µA) 0.04 0.02 0 -0.02 REGULATOR MODE -0.04 MAX19507 toc32 0.06 60 INPUT CURRENT vs. COMMON-MODE VOLTAGE GAIN ERROR vs.
PAGE 12
MAX19507 Dual-Channel, 8-Bit, 130Msps ADC Pin Description PIN NAME 1, 12, 13, 48 AVDD 2 CMA Channel A Common-Mode Input-Voltage Reference 3 INA+ Channel A Positive Analog Input 12 FUNCTION Analog Supply Voltage. Bypass each AVDD input pair (1, 48) and (12, 13) to GND with 0.1µF. 4 INA- Channel A Negative Analog Input 5 SPEN Active-Low SPI Enable. Drive high to enable parallel programming mode. 6 REFIO Reference Input/Output. To use internal reference, bypass to GND with a > 0.
PAGE 13
Dual-Channel, 8-Bit, 130Msps ADC PIN NAME FUNCTION 40 D5A Channel A Three-State Digital Output, Bit 5 41 D6A Channel A Three-State Digital Output, Bit 6 42 D7A Channel A Three-State Digital Output, Bit 7 (MSB) 43 DORA Channel A Data Over Range 44 DCLKA Channel A Data Clock 45 SDIN/FORMAT 46 SCLK/DIV Serial Clock/Clock Divider. Serial clock when SPEN is low. Clock divider when SPEN is high. 47 CS/OUTSEL Serial-Port Select/Data Output Mode. Serial-port select when SPEN is low.
PAGE 14
MAX19507 Dual-Channel, 8-Bit, 130Msps ADC CLOCK MAX19507 INA+ T/H INA- PIPELINE ADC DIGITAL ERROR CORRECTION D0A–D7A DORA DCLKA CMA REFIO CMB REFERENCE AND BIAS SYSTEM INTERNAL REFERENCE GENERATOR PIPELINE ADC DIGITAL ERROR CORRECTION DATA AND OUTPUT FORMAT OUTPUT DRIVERS OVDD (1.8V TO 3.3V) D0B–D7B INB+ T/H INB- DORB DCLKB CLOCK CLK+ CLOCK DIVIDER CLK- DUTYCYCLE EQUALIZER SYNC AVDD (1.8V OR 2.5V TO 3.3V) REGULATOR AND POWER CONTROL 1.
PAGE 15
Dual-Channel, 8-Bit, 130Msps ADC DECODER INTERNAL GAIN—BYPASS REFIO EXTERNAL GAIN CONTROL—DRIVE REFIO 36kΩ 0.1µF EXTERNAL BYPASS REFIO 1.250V BANDGAP REFERENCE 10kΩ BUFFER 23/32 AVDD CS SCLK SDIN TO CONTROL LOGIC 156kΩ SCALE AND INTERNAL REFERENCE LEVEL SHIFT (CONTROLS ADC GAIN) 3/32 AVDD Figure 4. Simplified Reference Schematic Figure 5. Simplified Parallel-Interface Input Schematic Table1.
PAGE 16
MAX19507 Dual-Channel, 8-Bit, 130Msps ADC CS SCLK R/W SDIN A6 A5 A4 R/W A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 DATA WRITE OR READ ADDRESS 0 = WRITE 1 = READ Figure 6. Serial-Interface Communication Cycle tCSH tCSS CS tSCLK SCLK tSDS tSDH tSDD SDIN WRITE READ Figure 7. Serial-Interface Timing Diagram Serial Programming Interface A serial interface programs the MAX19507 control registers through the CS, SDIN, and SCLK inputs.
PAGE 17
Dual-Channel, 8-Bit, 130Msps ADC ters are reset to default values. A read operation of register 0Ah returns a status byte with information described in Table 2. Table 2. Register 0Ah Status Byte BIT NO.
PAGE 18
MAX19507 Dual-Channel, 8-Bit, 130Msps ADC In addition to power management, the HPS_SHDN1 and HPS_SHDN0 activate an A+B adder mode. In this mode, the results from both channels are averaged. The MUX_CH bit selects which bus the (A+B)/2 data is presented.
PAGE 19
Dual-Channel, 8-Bit, 130Msps ADC BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 X X X X PD_DOUT_1 PD_DOUT_0 DIS_DOR DIS_DCLK Bit 7–4 Don’t care Bit 3, 2 PD_DOUT_1, PD_DOUT_0: Power-down digital output state control 00 = Digital output three state (default) 01 = Digital output low 10 = Digital output three state 11 = Digital output high Bit 1 DIS_DOR: DOR driver disable 0 = DOR active (default) 1 = DOR disabled (three state) Bit 0 DIS_DCLK: DCLK driver disable 0 = DCLK active (defaul
PAGE 20
MAX19507 Dual-Channel, 8-Bit, 130Msps ADC Data/DCLK Timing (03h) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 DA_BYPASS DLY_HALF_T DCLKTIME_2 DCLKTIME_1 DCLKTIME_0 DTIME_2 DTIME_1 DTIME_0 Bit 7 DA_BYPASS: Data aligner bypass 0 = Nominal (default) 1 = Bypasses data aligner delay line to minimize output data latency with respect to the input clock.
PAGE 21
Dual-Channel, 8-Bit, 130Msps ADC BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 X X CT_DCLK_2_A CT_DCLK_1_A CT_DCLK_0_A CT_DATA_2_A CT_DATA_1_A CT_DATA_0_A Bit 7, 6 Don’t care Bit 5, 4, 3 CT_DCLK_2_A, CT_DCLK_1_A, CT_DCLK_0_A: CHA DCLK termination control 000 = 50Ω (default) 001 = 75Ω 010 = 100Ω 011 = 150Ω 1xx = 300Ω Bit 2, 1, 0 CT_DATA_2_A, CT_DATA_1_A, CT_DATA_0_A: CHA data output termination control 000 = 50Ω (default) 001 = 75Ω 010 = 100Ω 011 = 150Ω 1xx = 300Ω CHB Data Output Ter
PAGE 22
MAX19507 Dual-Channel, 8-Bit, 130Msps ADC Clock Divide/Data Format/Test Pattern (06h) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 TEST_PATTERN TEST_DATA FORMAT_1 FORMAT_0 TERM_100 SYNC_MODE DIV1 DIV0 Bit 7 TEST_PATTERN: Test pattern selection 0 = Ramps from 0 to 255 (offset binary) and repeats (subsequent formatting applied) (default) 1 = Data alternates between D[7:0] = 01010101, DOR = 1, and D[7:0] = 10101010, DOR = 0 on both channels Bit 6 TEST_DATA: Data test mode 0 = Normal data
PAGE 23
Dual-Channel, 8-Bit, 130Msps ADC BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 CMI_SELF_B CMI_ADJ_2_B CMI_ADJ_1_B CMI_ADJ_0_B CMI_SELF_A CMI_ADJ_2_A CMI_ADJ_1_A CMI_ADJ_0_A Bit 7 CMI_SELF_B: CHB connect input common-mode to analog inputs 0 = Internal common-mode voltage is NOT applied to inputs (default) 1 = Internal common-mode voltage applied to analog inputs through 2kΩ resistors Bit 6, 5, 4 CMI_ADJ_2_B, CMI_ADJ_1_B, CMI_ADJ_0_B: CHB input common-mode voltage adjustment 000 = 0.
PAGE 24
MAX19507 Dual-Channel, 8-Bit, 130Msps ADC Clock Inputs 100Ω TERMINATION (PROGRAMMABLE) CLK+ The input clock interface provides for flexibility in the requirements of the clock driver. The MAX19507 accepts a fully differential clock or single-ended logic-level clock. For differential clock operation, connect a differential clock to the CLK+ and CLK- inputs. In this mode, the input common mode is established internally to allow for AC-coupling.
PAGE 25
Dual-Channel, 8-Bit, 130Msps ADC MAX19507 MUX OUTPUT MODE SAMPLING INSTANT tAD SAMPLING INSTANT SAMPLING INSTANT SAMPLING INSTANT SAMPLING INSTANT SAMPLING INSTANT IN_ tCLK n tCL tCH SAMPLE ON RISING EDGE n+1 n+2 n+3 n+4 n+5 SAMPLE CLOCK tCHA tDD DATA, DOR tCHB CHB CHA CHB CHA CHB CHA CHB CHA CHB CHA CHB CHA CHB n-10 n-9 n-9 n-8 n-8 n-7 n-7 n-6 n-6 n-5 n-5 n-4 n-4 tDC tHOLD tDCH tDCL tSETUP tHOLD tSETUP DCLK SAMPLE CLOCK IS THE DERIVED CLOCK FROM (CLK+
PAGE 26
MAX19507 Dual-Channel, 8-Bit, 130Msps ADC tHO DIVIDE-BY-2 SLIP SYNCHRONIZATION tSUV tSUV = SET-UP TIME FOR VALID CLOCK EDGE. tHO = HOLD-OFF TIME FOR INVALID CLOCK EDGE.
PAGE 27
Dual-Channel, 8-Bit, 130Msps ADC MAX19507 tHO DIVIDE-BY-2 EDGE SYNCHRONIZATION tSUV tSUV = SET-UP TIME FOR VALID CLOCK EDGE. tHO = HOLD-OFF TIME FOR INVALID CLOCK EDGE.
PAGE 28
MAX19507 Dual-Channel, 8-Bit, 130Msps ADC Table 4. Data Timing Controls DATA TIMING CONTROL DESCRIPTION DA_BYPASS Data aligner bypass. When this control is active (high), data and DCLK delay is reduced by approximately 3.4ns (relative to DA_BYPASS = 0). DLY_HALF_T When this control is active, data output is delayed by half clock period (T/2). This control does not delay data output if MUX mode is active.
PAGE 29
Dual-Channel, 8-Bit, 130Msps ADC MAX19507 fig13 VOVDD = 1.8V DA_BYPASS = 0 1.5 1.0 +10/16 +8/16 +6/16 +2/16 0 -2/16 0.5 0 70 80 90 100 110 120 RECOMMENDED DATA TIMING vs. SAMPLE RATE MAX19507 fig15 2.0 +11/16 +9/16 +7/16 +5/16 +3/16 +1/16 -1/16 -3/16 DATA DELAY (T FRACTIONAL PERIOD) DATA DELAY (T FRACTIONAL PERIOD) 2.0 VOVDD = 1.8V DA_BYPASS = 1 1.5 +11/16 +9/16 +7/16 +5/16 +3/16 +1/16 -1/16 -3/16 1.0 0.5 70 +2/16 0 -2/16 80 90 100 110 120 130 SAMPLING RATE (Msps) Figure 13.
PAGE 30
MAX19507 Dual-Channel, 8-Bit, 130Msps ADC Table 7. Recommended Timing Adjustments (VOVDD = 3.3V) SAMPLING RATE (Msps) VOVDD = 3.3V FROM TO DA_BYPASS DLY_HALF_T DTIME<2:0> DCLKTIME<2:0> 65 73 1 0 000 000 73 88 1 0 101 101 88 103 1 0 110 110 103 118 1 0 111 111 118 130 1 1 011 011 Table 8.
PAGE 31
Dual-Channel, 8-Bit, 130Msps ADC MAX19507 AVDD (PINS 1, 12, 13, 48) REGULATOR IN 2.3V TO 3.5V OUT 1.8V ENABLE INTERNAL ANALOG CIRCUITS REFERENCE GND Figure 17. Integrated Voltage Regulator Applications Information Analog Inputs IN_+ 0.1µF 1 VIN 6 36.5Ω 0.5% MAX19507 T1 N.C. 5 2 Transformer-Coupled Differential Analog Input The MAX19507 provides better SFDR and THD with fully differential input signals than a single-ended input drive.
PAGE 32
MAX19507 Dual-Channel, 8-Bit, 130Msps ADC VIN 0.1µF 0.01µF IN_+ MAX4108 CLK+ 0.1µF CLKIN 100Ω 49.9Ω MAX19507 MAX19507 CM_ 100Ω 0.1µF 49.9Ω 0.01µF CLK- IN_0.1µF Figure 20. Single-Ended, AC-Coupled Input Drive Figure 21. Single-Ended-to-Differential Clock Input The circuit of Figure 19 also converts a single-ended input signal to a fully differential signal.
PAGE 33
Dual-Channel, 8-Bit, 130Msps ADC Single-Tone Spurious-Free Dynamic Range (SFDR1 and SFDR2) SFDR is the ratio expressed in decibels of the RMS amplitude of the fundamental (maximum signal component) to the RMS amplitude of the next largest spurious component, excluding DC offset. SFDR1 reflects the spurious performance based on worst 2nd-order or 3rd-order harmonic distortion. SFDR2 is defined by the worst spurious component excluding 2nd- and 3rdorder harmonics and DC offset.
PAGE 34
Dual-Channel, 8-Bit, 130Msps ADC OVDD D2B D3B D4B D5B D6B D7B I.C. I.C. D1A OVDD TOP VIEW D0A MAX19507 Pin Configuration 36 35 34 33 32 31 30 29 28 27 26 25 D2A 37 24 D1B D3A 38 23 D0B D4A 39 22 I.C. D5A 40 21 I.C. D6A 41 20 DCLKB D7A 42 19 DORB DORA 43 18 GND GND MAX19507 DCLKA 44 17 SDIN/FORMAT 45 16 CLK- SCLK/DIV 46 15 CLK+ 14 SYNC 13 AVDD 8 9 10 11 12 INB- CMB 7 AVDD 6 I.C.
PAGE 35
Dual-Channel, 8-Bit, 130Msps ADC REVISION NUMBER REVISION DATE 0 10/08 Initial release 1 9/10 Updated timing characteristics based on CMOS output driver changes DESCRIPTION PAGES CHANGED — 5, 6, 28, 29, 30 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.