Datasheet

MAX191
Low-Power, 12-Bit Sampling ADC
with Internal Reference and Power-Down
_______________________________________________________________________________________ 5
PARAMETER
SCLK to SCLK
OUT
Delay
CONDITIONS
160
UNITS
ns
CS to DOUT Three-State
100 ns
SYMBOL
CS or RD Setup Time
CS or RD Hold Time
ns
150 ns
t
20
t
19
t
17
t
16
TIMING CHARACTERISTICS (Figures 6–10) (continued)
(V
DD
=5V ±5%, V
SS
= 0V or -5V ±5%, T
A
= T
MIN
to T
MAX
, unless otherwise noted.) (Note 14)
10
MAX191C/E
MIN TYP MAX
180
110
10
150
MAX191M
MIN TYP MAX
200
120
10
150
310 350SCLK to SSTRB Delay 260 nst
23
260 280SCLK to DOUT Delay 240 nst
22
130SCLK
OUT
to DOUT Delay 100 nst
21
150
Note 1: Performance at power-supply tolerance limits guaranteed by power-supply rejection test.
Note 2: V
DD
= 5V, V
SS
= 0V, FS = VREF.
Note 3: FS = VREF, offset nulled, ideal last-code transition = FS - 3/2 LSB.
Note 4: Gain-Error Tempco = ∆GE is the gain-error change from T
A
= +25°C to T
MIN
or T
MAX
.
Note 5: Conversion time defined as the number of clock cycles times the clock period; clock has a 50% duty cycle.
Note 6: Guaranteed by design, not production tested.
Note 7: AIN+, AIN- must not exceed supplies for specified accuracy.
Note 8: VREF TC = ∆T, where ∆VREF is reference-voltage change from T
A
= +25°C to T
MIN
or T
MAX
.
Note 9: Output current should not change during conversion. This current is in addition to the current required by the internal DAC.
Note 10: REFADJ adjustment range is defined as the allowed voltage excursion on REFADJ relative to its unadjusted value of 2.4V.
This will typically result in a 1.7 times larger change in the REF output (Figure 19a).
Note 11: This current is included in the PD supply current specification.
Note 12: Floating the PD pin guarantees external compensation mode.
Note 13: V
REF
= 4.096V, external reference.
Note 14: All input control signals are specified with t
r
= t
f
= 5ns (10% to 90% of 5V) and timed from a voltage level of 1.6V.
Note 15: t
3
and t
6
are measured with the load circuits of Figure 1 and defined as the time required for an output to cross 0.8V or 2.4V.
Note 16: t
7
is defined as the time required for the data lines to change 0.5V when loaded with the circuits of Figure 2.
T
A
= +25°C
MIN TYP MAX