9-4506; Rev 2, 4/95 MAXIMA RECOMMENDED FOR NEW DESIGNS WV AX1L/WVI Low-Power, 12-Bit Sampling Ad Cs with Internal Reference and Power-Down General Description The MAX190/MAX181 are monolithic, COS, 12-bit analog-to-digital converters (Ad Cs) featuring differential inputs, trackball internal voltage reference, internal or textual clock, and parallel or serial uP interface. Both devices have a 7.5us conversion time.
Low-Power, 12-Bit Sampling Ad Cs with Internal Reference and Power-Down ELECTRICAL CHARACTERISTICS (continued) (Toss = SV 45%, Vis (MAX191T only), fox = 1.6MHz, 50% duty cycle. AINU AND. BIP = GND, sow-memory mode, i once rode. teleconference compensation mode. synchronous operation, Figure 6. Ta = Taine to Tax. unless anywise noted.
MAX190/MAX191 Low-Power, 12-Bit Sampling Ad Cs with Internal Reference and Power-Down ELECTRICAL CHARACTERISTICS (continued) (VDD (MAXIMA only), foi K = 1.6M12, 50% duly cycle, AINU AND. BI = GND, slow mode, internet deterrence mode, external-referance compensation mode, synchronous operation. Figure 6. Ta = Than to Parthia, unless otherwise noted.
Low-Power, 12-Bit Sampling Ad Cs with Internal Reference and Power-Down TIMING CHARACTERISTICS (see Figures 6-10) (continued) (Vp = BY 15%. Vig (MAX 191 only). Ta = Thins fo Wax, unless otherwise noted.) (Note 14) Ta=425'C MAX1a__C/E MAXIMA PARAMETER SYMBOL | CONDITIONS — UNITS MIN TYP MAX MIN TYP MAX | MIN TYP MAX Simon 0SSTRB se |, 100 130 150 our S578 ne Jon 50 150 | ne Bor FE Hoa Tim . MAX 190 fil) Solo Time uae Delay i. an .
MAX190/MAX191 Low-Power, 12-Bit Sampling Ad Cs with Internal Reference and Power-Down Typical Operating Characteristics CLOCK FREQUENCY POWER-DOWN SUPPLY CURRENT NEGATIVE SUPPLY CURRENT vs. TIMING CAPACITOR vs. TEMPERATURE vs. TEMPERATURE (MAXIMA ONLY) Iss (MAX 191 ORLY] » heme lone S20 Be = THING CAPACITOR (oF) TEMPERATURE POSITIVE SUPPLY CURRENT vs. TEMPERATURE MAXIMA FFT PLOT kHz 5.608 FREQUENCY 12] TEMPERATURE CO) MAXIMA FFT PLOT KHz $6.
Low-Power, 12-Bit Sampling Ad Cs with Internal Reference and Power-Down Pin Description PIN NAME FUNCTION MAXIMA MAXIMA Power-Down input. Alaric low ai PD deaves the ADC only the band gap reference ogc high selects normal operation, internal-reference Cong ion made. An ope: condition sel normal operation, external-reference compensation mode 2 AND Analog Ground Connect both AND pins 0 ground 2 vss Negative Supply Input, OV fo 5.258 a 3 Ainu Sampled Analog Input 4 4 Analogize Input Return.
MAX190/MAX191 Low-Power, 12-Bit Sampling Ad Cs with Internal Reference and Power-Down 5 High-Z 10 Voi and Vou to Var Figure 1. Load Circus for Access Time Us o EDGE 9. Vita High Z 26 02010) Vs (MEK) 2 WAY saves ax190 i Maxima t 4P DATERS NOTE: £1 120pF GENERATES {NIH NOMINAL CLOCK Figure 2. Load Circuits for Bus-Relinquish Time Detailed Description The MAX 1S0/MAX191 use successive approximation and input track/mold (TAH) circuitry to convert an analog input signal 10 a 12-bit digital output.
Low-Power, 12-Bit Sampling Ad Cs with Internal Reference and Power-Down TRACK a COMPARATIVE Atl: wn r Tex ADDENDUM MAX 190 o |. MAX! 2 ag NOTE: {pi » 14 165 The NO ANAL C10CK Figure 4. Equivalent fr gut Circuit The time required for the TH to acquire an input signal is function of how quickly its input capacitance is charged If the input signal's source impedance is high, the acquisition Hume ginseng and more time must be allowed between conversions.
MAX190/MAX191 Low-Power, 12-Bit Sampling Ad Cs with Internal Reference and Power-Down Clock and Control Synchronization For best analog performance on the MAX190/MAX191, the clock should be synchronized to the conversion start signals (CS and RD) as shown in Figure 8. At least 100ns should separate the start of a conversion from the nearest clock edge. This ensures that CLK transitions are not coupled to the analog input and sampled by the TH.
Low-Power, 12-Bit Sampling Ad Cs with Internal Reference and Power-Down MAXIMA Asynchronous Mode The above precautions for the MAXIMA are not necessary on the MAX 131. since conversion always begin on the falling edge of the clock. Parallel Digital-interface Mode Output-Data Format The data output from the MAX 190MAX 191 is straight binary in the uni polar mode. In the bipolar mode, the MSB is inverted (see Figure 22). The 12 data bits can be output either in two 8-lib bytes or as a serial cutout.
MAX190/MAX191 Low-Power, 12-Bit Sampling Ad Cs with Internal Reference and Power-Down HEN ¥ £5 OLE DATA 07-00 we] CATS ee— Ee HOLD® «= om TRACK “INTERNAL SIGNAL TRACKING INPUT SIGNAL WHEN HOLD = Low. HOLDING WHEN HOLD = gr 7. Slow-Memory Mode. 2-Byte Read Data-Bus Status HEN DATA 92-00 = NEW DATA AT ot 071-08 AD TRACK INTERNAL SIGNAL TRACKING INPUT SIGNAL WHEN HOLD = Low HOLDING WHEN HOU = sgn Figure 8.
Low-Power, 12-Bit Sampling Ad Cs with Internal Reference and Power-Down HEN 1x eer TS 5 an RST DATA ee 4g i ble ely ant HANK “INTERNAL SIGNAL TACKING INPUT SIGNAL WHEN HOLD » Law, HOLDING WHEN HOLD High NEW DATA 07.08 Newtonian [1108 Figure 9 ROM Mode, 2:8yte deaf within One Conversion Timing Diagram 501K THREE STATE cou / THREE TEASE THEE STATE SUE ORLY APPLIES IF A CONVERSATION STARTS WHILE SEES 1DW. Figure 10a.
Low-Power, 12-Bit Sampling Ad Cs with Internal Reference and Power-Down Table 1. Data-Bus Output, Low PIN NAME FOLDOUT Walkout DISTRESS D4 Dams D2D10 D1/Dg Droid HEN = (3, PAR PARALLEL MODE HEN = 1, PAR PARALLEL MODE Low aw Low Low O11 Dw Dg 08 ENT EY DOUR | scour | STRABO Low Low Low Low Low HEN = X, PAR = 0, Three SERIAL MODE, Ab = 1 POUT Stated Stared Low Low Low Low Low Note: are the ADC data output pins, DOUR = Tyre CLIP IN serial mode D-pit conversion results. 1st the MSE.
Low-Power, 12-Lit Sampling Ad Cs with Internal Reference and Power-Down Maximum Clock Rate in Serial Mode The maximum SILK rate depends on the minimum set-up time required at the serial data input to the uP and the ADC's DOUR to SILK delay (122) (see Figure 12). The maximum fascia is as follows: fai (MAX) = (1/2) x + 122) where patsy) is the minimum data seal-up time “required .. the serial data input 10 the uP. For example, Molester's MOB8HC11A8 data book specifies a 100ns minimum data setup time.
MAX190/MAX191 Low-Power, 12-Bit Sampling Ad Cs with Internal Reference and Power-Down CAIAPHAS} Setting CLOP = 1 and CHAP = 1 starts the clock high during a read instruction. Both the MAXIMA and MAXIMA will shift out a leading 0 followed by the 12 data bits and three trailing Os (Figure 140} SPIV Unlike SPI, which requires two 1-byte reads to acquire the 12 bits of data from the ADC, SPIV allows the minimum number of clock cycles required to clock in the data.
Low-Power, 12-Bit Sampling Ad Cs with Internal Reference and Power-Down THREE STATE Tie MEE (ise Si Ate 2 MAXIMA, CFOL=0. CF HA = 0 Bou sth SNINSNSNNSNSS\NSNNT [3 | | THREE | STATE THEE wat Si If b. WAXWING POOL = 0, OPA FH ANS A KANA ANNAM = EXIT YEE sou i X 1 LPG 1, 0 Figure 15. 0S, * Striae-interface Timing SIRE | | TALE 1 | STATE Dov Aer CEE Xen Xon )C UT XT DEX Be XC CRE XR XT XE Figure 1.
MAX190/MAX191 Low-Power, 12-Bit Sampling Ad Cs with Internal Reference and Power-Down Applications Information Power-Down Mode/Initialization After Power-Up In some battery-powered systems, it is desirable to power down or remove power from the ADC during inactive periods. To power down the MAX190/MAX 191, drive PD low.
Low-Power, 12-Bit Sampling Ad Cs with Internal Reference and Power-Down Rl i COUNTERSIGNS PER SECOND Figure 185. Low Average-Power Mode Operation (Internal Com. Figure 180. Average Supply Gi 5. Conversion ate, Pow sensation) External Compensation Figure 19a shows the connection for external compensation with reference adjustment. In this mode. an external 4.7uF capacitor compensates the reference output am amplifier, allowing for maximum conversion speed and lowest conversion noise.
MAX190/MAX191 Low-Power, 12-Bit Sampling Ad Cs with Internal Reference and Power-Down Law Average-Power Mods Sheraton (External J I both offset and fll scale need adjustment, the circuit in Figure 21b is recommended. For single-supply Ad Cs, it is virtually impossible to nil system negative offset errors. However, the MAX190/MAX 191 input configuration is pseudo-differential — only the difference in voltage between AINU and Willing be convened into its digital representation.
Low-Power, 12-Bit Sampling Ad Cs with Internal Reference and Power-Down mam R7 MAXIMA Maxilla MAXINE MAXI! HE MAXIMA OPERATED FROM 35% Figure 210. Offset (£10mV) and Gain (1%) Tim Cree Digital Bus Noise if the data us connected to the ADC is active during a conversion, crosswalk from the data pins to the ADC comparative hay generate errors, Slow-memory mode avoids this problem by placing the §P in a wait state during the conversion.
MAX190/MAX191 Low-Power, 12-Bit Sampling Ad Cs with Internal Reference and Power-Down High-frequency noise in the Vop power supply may affect the high-speed comparative in the ADC. Bypass these supplies to the single-point analog ground with 0.01pfF ard 10uF bypass capacitors. Minimize capacitor lead lengths for best supply-noise rejection. If the +5Y power supply 1s very noisy, a 108 resistor can he connected as a low pass filter to filter out supply noise (Figure 23).
Low-Power, 12-Bit Sampling Ad Cs with Internal Reference and Power-Down Package Information 0.250.40.005 LEAD #1 20-0110 ~ 0762-2758) MAB > Ba 010-0320 0,13 £000 se2 Corine 7620-8. 0.606 -0.015 8.820. oan lL LES L01z000 E Was comm THY & a [ori (sas 350) 24 Lead Plastic Narrow DIP 05 = 120°C/W 8)c = BOCK LEAD #1 oO ARR ——F pa ASHE Al ch EEE LLL a] lest use 9.014 -0.019 355 ~ 0.482) 337-2642) — A812 { « s.5a5) WX [HEEL Mm Jo i S55 wn aa fms 0am J 0.
MAX190/MAX191 Low-Power, 12-Bit Sampling Ad Cs with Internal Reference and Power-Down Package Information [continued) MAXI [Mo ar ASE ee — HH Main 1 ed Products Printed USA AKIMBO is a registered ta
