Datasheet

MAX17094
Internal-Switch Boost Regulator with Integrated
7-Channel Driver, VCOM Calibrator, Op Amp, and LDO
8 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(V
IN
= V
LIN
= V
EN
= +3.3V, circuit of Figure 2, V
MAIN
= 8V, V
GON1
= V
GON2
= 21V, V
GOFF
= -6.5V. T
A
= -40°C to +85°C, unless oth-
erwise noted.) (Note 3)
PARAMETER CONDITIONS MIN TYP MAX UNITS
INPUT-VOLTAGE DETECTOR
SENSE Voltage Range V
VL
V
SENSE Threshold Voltage Falling edge, 10mV (typ) hysteresis 1.200 1.270 V
PROGRAMMABLE VCOM CALIBRATOR
GON2 Calibrator Threshold Rising edge, 230mV hysteresis 7 8.5 10.5 V
GON1 Voltage Threshold to
Enable Program
Rising edge, 230mV hysteresis 7 10.5 V
GON2 Input-Voltage Range 11 30 V
SET Voltage Resolution 7 Bits
SET Differential Nonlinearity -1 +1 LSB
SET Zero-Scale Error -1 +1 +3 LSB
SET Full-Scale Error -4 +5 LSB
SET Current 120 μA
To GND, V
AVDD
= 14V 8.5 170 k
SET External Resistance
To GND, V
AVDD
= 6V 2.5 50 k
Memory Write Cycles 30 Times
Memory Write Time R
FREQ
= unconnected 150 ms
I
2
C INTERFACE
Logic-Input Low Voltage (V
IL
) SDA, SCL
0.3 x V
IN
V
Logic-Input Low Voltage ADDR0, ADDR1
0.2 x V
IN
V
Logic-Input High Voltage (V
IH
) SDA, SCL, ADDR0, ADDR1
0.7 x V
IN
V
SDA Output Low Voltage I
SDA
= -3mA sink 0 0.4 V
SDA and SCL Input Capacitance SDA, SCL (Note 1) 10 pF
SCL Frequency (f
SCL
) DC 400 kHz
SCL High Time (t
HIGH
) 600 ns
SCL Low Time (t
LOW
) 1300 ns
SDA and SCL Rise and Fall Time
(t
R
, t
F
)
Cb = total capacitance of bus line in pF (Note 1)
20 + 0.1
x Cb
300 ns
START Condition Hold Time
(t
HD:STA
)
10% of SDA to 90% of SCL 600 ns
START Condition Setup Time
(t
SU:STA
)
600 ns
Data Input Hold Time (t
HD:DAT
) 50 ns
Data Input Setup Time (t
SU:DAT
) 100 ns
STOP Condition Setup Time
(t
SU:STO
)
600 ns
Bus Free Time (t
BUF
) 1300 ns
SDA Capacitive Loading (Cb) (Note 2) 400 pF
Input Filter Spike Suppression SDA, SCL, not tested 50 ns