Datasheet

Table 3 lists the WR values and the corresponding I
SET
,
V
SET
, and V
OUT
values.
Access Control Register (ACR) 02h
The register select bit (RSB) is the most significant bit
of the byte stored in the ACR and is used to select
whether WR or IVR is accessed during read and write
cycles involving the data register.
When writing to the data register, if RSB is set to 1, only
WR is updated with the value written to the data register.
If RSB is set to 0, both WR and IVR are updated with the
value written that was written to the data register.
When reading the data register, if RSB is set to 1, the
value read from the data register is from WR: otherwise,
if RSB is set to 0, the value read from the data register
is from IVR.
When configuring RSB, only 00h or 80h should be writ-
ten to the ACR to set RSB to 0 or 1, respectively, in
order to keep all bits other than the RSB bit in the ACR
to zeros. The ACR comprises volatile memory, which is
preset to 00h during power-up. Figure 10 shows the
ACR byte.
Write Operation
To perform a write operation, the master must generate
a START condition, write the slave address byte (R/W =
0), write the register address, write the byte of data,
and generate a STOP condition. When writing to the
WR/IVR register, the potentiometer adjusts to the new
setting once it has acknowledged the new data has
been written to WR. If the ACR is set such that both WR
and IVR are to be updated with the value written to the
WR/IVR register, a write cycle is performed first to
update WR, followed by an internal write cycle to
update IVR. The SCL and SDA lines are ignored until
the internal IVR write cycle has finished. Figure 11
shows the write operation.
Read Operation
To perform a read operation, the master generates a
START condition, writes the slave address byte (R/W =
0), writes the register address, generates a repeated
START condition, writes the slave address byte (R/W =
1), reads data with ACK or NACK as applicable, and
generates a STOP condition. Figure 12 shows a read
operation.
MAX17094
Internal-Switch Boost Regulator with Integrated
7-Channel Driver, VCOM Calibrator, Op Amp, and LDO
______________________________________________________________________________________ 25
Table 3. DAC Settings
7-BIT
VCOM DATA
BYTE
I
SET
V
SET
(V) V
OUT
(V)
0000000 I
SET(MAX)
V
SET(MAX)
V
MIN
0000001
I
SET(MAX)
-
1 LSB
V
SET(MAX)
-
1 LSB
V
MIN
+
1 LSB
.
.
.
.
.
.
.
.
.
.
.
.
1111110
I
SET(MIN)
+
1 LSB
V
SET(MIN)
+
1 LSB
V
MAX
-
1 LSB
1111111 I
SET(MIN)
V
SET(MIN)
V
MAX
MSB LSB
RESERVED
b7 0 0 0
0
0
0
0
REGISTER
SELECT
BIT (RSB)
Figure 10. Access Control Register Byte
START
0 01 1 0
A1 A2
0
STOP
b7 b6
b5 b4
b3 b2 b1 b0
SLAVE
ACK
SLAVE
ACK
b7 b6
b5 b4
b3 b2 b1
b0
SLAVE
ACK
MSB LSB
MSB
LSB
MSB
LSB
SLAVE
ADDRESS*
READ/WRITE
*THE SLAVE ADDRESS IS DETERMINED BY ADDRESS PINS ADDR0 AND ADDR1.
REGISTER ADDRESS DATA
Figure 11. Write Operation
0 01 1 0
A1 A2
STOP
b7 b6
b5 b4
b3 b2
b1
1
SLAVE
ACK
START
REPEATED
START
0
0 0
1
1
0
A1 A2
1
SLAVE
ADDRESS*
READ/
WRITE
b6
b5 b4
b3 b2
b1
b7
b0
*THE SLAVE ADDRESS IS DETERMINED BY ADDRESS PINS ADDR0 AND ADDR1.
MSB LSB LSB
MSB
MSB LSB
MSB
LSB
REGISTER ADDRESS SLAVE
ADDRESS*
READ/WRITE DATA
SLAVE
ACK
SLAVE
ACK
MASTER
NACK
Figure 12. Read Operation