Datasheet

MAX16936
36V, 220kHz to 2.2MHz Step-Down Converter
with 28µA Quiescent Current
14Maxim Integrated
and ESR is lower than the desired closed-loop crossover
frequency. To stabilize a nonceramic output capacitor
loop, add another compensation capacitor (C
F
) from
COMP to GND to cancel this ESR zero.
The basic regulator loop is modeled as a power modulator,
output feedback divider, and an error amplifier. The power
modulator has a DC gain set by g
m
O R
LOAD
, with a pole and
zero pair set by R
LOAD
, the output capacitor (C
OUT
), and its
ESR. The following equations allow to approximate the value
for the gain of the power modulator (GAIN
MOD(dc)
), neglect-
ing the effect of the ramp stabilization. Ramp stabilization is
necessary when the duty cycle is above 50% and is
internally done for the device.
MOD(dc) m LOAD
GAIN g R= ×
where R
LOAD
= V
OUT
/I
LOUT(MAX)
in I and g
m
= 3S.
In a current-mode step-down converter, the output
capacitor, its ESR, and the load resistance introduce a
pole at the following frequency:
= π× ×
pMOD OUT LOAD
f 1(2 C R )
The output capacitor and its ESR also introduce a zero at:
zMOD
OUT
1
f
2 ESR C
=
π× ×
When C
OUT
is composed of “n” identical capacitors in
parallel, the resulting C
OUT
= n O C
OUT(EACH)
, and ESR
= ESR
(EACH)
/n. Note that the capacitor zero for a paral-
lel combination of alike capacitors is the same as for an
individual capacitor.
The feedback voltage-divider has a gain of GAIN
FB
= V
FB
/
V
OUT
, where V
FB
is 1V (typ). The transconductance error
amplifier has a DC gain of GAIN
EA(dc)
= g
m
,
EA
O R
OUT,EA
,
where g
m,EA
is the error amplifier transconductance,
which is 700FS (typ), and R
OUT,EA
is the output resis-
tance of the error amplifier 50MI.
A dominant pole (f
dpEA
) is set by the compensation
capacitor (C
C
) and the amplifier output resistance
(R
OUT,EA
). A zero (f
zEA
) is set by the compensation
resistor (R
C
) and the compensation capacitor (C
C
).
There is an optional pole (f
pEA
) set by C
F
and R
C
to
cancel the output capacitor ESR zero if it occurs near
the cross over frequency (f
C
, where the loop gain equals
1 (0dB)). Thus:
dpEA
C OUT ,E A C
zEA
CC
pEA
FC
2 C (R R )
2C R
2CR
π× × +
π× ×
π× ×
The loop-gain crossover frequency (f
C
) should be set
below 1/5th of the switching frequency and much higher
than the power-modulator pole (f
pMOD
):
SW
pMOD C
f
ff
5
<< ≤
The total loop gain as the product of the modulator gain,
the feedback voltage-divider gain, and the error amplifier
gain at f
C
should be equal to 1. So:
FB
MOD(fC) EA(fC)
OUT
V
GAIN GAIN 1
V
×× =
EA(fC) m, EA C
pMOD
MOD(fC) MOD(dc)
C
GAIN g R
f
GAIN GAIN
f
= ×
= ×
Therefore:
FB
MOD(fC) m,EA C
OUT
V
GAIN g R 1
V
× × ×=
Solving for R
C
:
OUT
C
m,EA FB MOD(fC)
V
R
g V GAIN
=
××
Set the error-amplifier compensation zero formed by R
C
and C
C
(f
zEA
) at the f
pMOD
. Calculate the value of C
C
a
follows:
C
pMOD C
1
C
2f R
=
π× ×
If f
zMOD
is less than 5 x f
C
, add a second capacitor,
C
F
, from COMP to GND and set the compensation pole
formed by R
C
and C
F
(f
pEA
) at the f
zMOD
. Calculate the
value of C
F
as follows:
F
zMOD C
1
C
2f R
=
π× ×