Datasheet

MAX1630–MAX1635
Multi-Output, Low-Noise Power-Supply
Controllers for Notebook Computers
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Table 4. Operating Modes
SEQ RUN/ON3 DESCRIPTION
XLow X All circuit blocks turned off. Supply current = 4µA.
SHDN
TIME/ON5
X
MODE
Shutdown
Low StandbyLowHigh Ref Both SMPSs off. Supply current = 30µA.
Low RunHigh
High RunLowHigh Ref 5V SMPS enabled/3.3V off
High Ref 3.3V SMPS enabled/5V off
High RunHigh
Timing capacitor StandbyLowHigh GND Both SMPSs off. Supply current = 30µA.
Timing capacitor RunHigh
Timing capacitor StandbyLowHigh VL Both SMPSs off. Supply current = 30µA.
High
High Ref Both SMPSs enabled
GND Both SMPSs enabled. 5V enabled before 3.3V.
Timing capacitor RunHighHigh VL Both SMPSs enabled. 3.3V enabled before 5V.
X = Don’t Care
Shutdown Mode
Holding SHDN low puts the IC into its 4µA shutdown
mode. SHDN is logic input with a threshold of about 1V
(the V
TH
of an internal N-channel MOSFET). For auto-
matic start-up, bypass SHDN to GND with a 0.01µF
capacitor and connect it to V+ through a 220kΩ resistor.
Power-Up Sequencing
and ON/
OFF Controls
Start-up is controlled by RUN/ON3 and TIME/ON5 in
conjunction with SEQ. With SEQ tied to REF, the two
control inputs act as separate ON/OFF controls for
each supply. With SEQ tied to VL or GND, RUN/ON3
becomes the master ON/OFF control input and
TIME/ON5 becomes a timing pin, with the delay
between the two supplies determined by an external
capacitor. The delay is approximately 800µs/nF. The
+3.3V supply powers-up first if SEQ is tied to VL, and
the +5V supply is first if SEQ is tied to GND. When driv-
ing TIME/ON5 as a control input with external logic,
always place a resistor (>1kΩ) in series with the input.
This prevents possible crowbar current due to the inter-
nal discharge pull-down transistor, which turns on in
standby mode and momentarily at the first power-up or
in shutdown mode.
RESET Power-Good Voltage Monitor
The power-good monitor generates a system RESET sig-
nal. At first power-up, RESET is held low until both the
3.3V and 5V SMPS outputs are in regulation. At this point,
an internal timer begins counting oscillator pulses, and
RESET continues to be held low until 32,000 cycles have
elapsed. After this timeout period (107ms at 300kHz or
160ms at 200kHz), RESET is actively pulled up to VL. If
SEQ is tied to REF (for separate ON3/ON5 controls), only
the 3.3V SMPS is monitored—the 5V SMPS is ignored.
Output Undervoltage Shutdown Protection
(MAX1630/MAX1631/MAX1632)
The output undervoltage lockout circuit is similar to
foldback current limiting, but employs a timer rather
than a variable current limit. Each SMPS has an under-
voltage protection circuit that is activated 6144 clock
cycles after the SMPS is enabled. If either SMPS output
is under 70% of the nominal value, both SMPSs are
latched off and their outputs are clamped to ground by
the synchronous rectifier MOSFETs (see Output
Overvoltage Protection section). They won’t restart until
SHDN or RUN/ON3 is toggled, or until V+ power is
cycled below 1V. Note that undervoltage protection can
make prototype troubleshooting difficult, since you
have only 20ms or 30ms to figure out what might be
wrong with the circuit before both SMPSs are latched
off. In extreme cases, it may be useful to substitute the
MAX1633/MAX1634/MAX1635 into the prototype
breadboard until the prototype is working properly.
Output Overvoltage Protection
(MAX1630/MAX1631/MAX1632)
Both SMPS outputs are monitored for overvoltage. If
either output is more than 7% above the nominal regu-
lation point, both low-side gate drivers (DL_) are
latched high until SHDN or RUN/ON3 is toggled, or until
V+ power is cycled below 1V. This action turns on the
synchronous rectifiers with 100% duty, in turn rapidly
discharging the output capacitors and forcing both
SMPS outputs to ground. The DL outputs are also kept
high whenever the corresponding SMPS is disabled,
and in shutdown if VL is sustained.