Datasheet

MAX1584/MAX1585
5-Channel Slim DSC Power Supplies
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to drive an N-channel MOSFET. Its feedback (FB1)
threshold is 1.25V.
AUX2
In the MAX1584, AUX2 is identical to AUX1.
In the MAX1585, AUX2 is an inverting controller that
generates a regulated negative output voltage, typically
for CCD and LCD bias. This is handy in height-limited
designs where transformers might not be desired.
The AUX2 MOSFET driver (DL2) in the MAX1585 is
designed to drive P-channel MOSFETs. DL2 swings
from GND to PVSU. See Figure 8 for a typical inverter
configuration.
AUX3 DC-DC Step-Down Controller
AUX3 can be used for conventional DC-DC step-down
(buck) designs (Figure 1). Its output (DL3) is designed to
drive a P-channel MOSFET and swings from GND to
PVSU. Its feedback (FB3) threshold is 1.25V.
Master/Slave Configurations
The MAX1584/MAX1585 support the MAX1801 slave
PWM controllers that obtain input power, a voltage ref-
erence, and an oscillator signal directly from the
MAX1584/MAX1585 master. The master/slave configu-
ration allows channels to be easily added and mini-
mizes system cost by eliminating redundant circuitry.
The slaves also control the harmonic content of noise
since their operating frequency is synchronized to that
of the MAX1584/MAX1585 master converter. A
MAX1801 connection to the MAX1584/MAX1585 is
shown in Figure 12.
Status Outputs ( SDOK , AUX1OK , SCF)
The MAX1584/MAX1585 include three versatile status
outputs that can provide information to the system. All
are open-drain outputs and can directly drive MOSFET
switches to facilitate sequencing, disconnect loads
during overloads, or perform other hardware-based
functions.
SDOK pulls low when the step-down has successfully
completed soft-start. SDOK goes high impedance in
shutdown, overload, and thermal limit. A typical use for
SDOK is to enable 3.3V power to the CPU I/O after the
CPU core is powered up (Figure 13), thus providing safe
sequencing in hardware without system intervention.
AUX1OK pulls low when the AUX1 controller has suc-
cessfully completed soft-start. AUX1OK goes high
impedance in shutdown, overload, and thermal limit. A
typical use for AUX1OK is to drive a P-channel MOSFET
that gates 5V power to the CCD until the +15V CCD bias
(generated by AUX1) is powered up (Figure 14).
SCF goes high (high impedance, open drain) when
overload protection occurs. Under normal operation,
SCF pulls low. SCF can drive a high-side P-channel
MOSFET switch that can disconnect a load during
power-up or when a channel turns off in response to a
logic command or an overload. Several connections
are possible for SCF. One is shown in Figure 15, where
SCF provides load disconnect for the step-up on fault
and power-up.
Soft-Start
The MAX1584/MAX1585 channels feature a soft-start
function that limits inrush current and prevents exces-
sive battery loading at startup by ramping the output
voltage of each channel up to the regulation voltage.
This is accomplished by ramping the internal reference
inputs to each channel error amplifier from 0V to the
1.25V reference voltage over a period of 4096 oscillator
cycles (16ms at 500kHz) when initial power is applied
or when a channel is enabled. Soft-start is not included
in the step-up converter in order to avoid limiting start-
up capability with loading.
The step-down soft-start ramp takes half the time (2048
clock cycles) of the other channel ramps. This allows
the step-down and AUX3 output (when set to 3.3V) to
track each other and rise at nearly the same dV/dt rate
on power-up. Once the step-down output reaches its
regulation point (1.5V or 1.8V typ), the AUX3 output
(3.3V typ) continues to rise at the same ramp rate.
Fault Protection
The MAX1584/MAX1585 have robust fault and overload
protection. After power-up, the device is set to detect
an out-of-regulation state that could be caused by an
overload or short. If any DC-DC converter channel
(step-up, step-down, or any of the auxiliary controllers)
remains faulted for 100,000 clock cycles (200ms at
500kHz), then all outputs latch off until the step-up DC-
DC converter is reinitialized by the ONSU pin or by
cycling the input power. The fault-detection circuitry for
any channel is disabled during its initial turn-on soft-
start sequence.
An exception to the standard fault behavior is that there
is no 100,000 clock-cycle delay in entering the fault
state if the step-up output (PVSU) is dragged below its
2.5V UVLO threshold or is shorted. The step-up UVLO
immediately triggers and shuts down all channels. The
step-up then continues to attempt to start. If the step-up
output short remains, these attempts do not succeed
since PVSU remains near ground.
If a soft-short or overload remains on PVSU, the startup
oscillator switches the internal N-channel MOSFET, but
fault is retriggered if regulation is not achieved by the