Datasheet

Interface Timing
Input/Output Mode, Multichannel Conversion
Timing
I/O mode is selected when the MODE input is open
circuit. In I/O mode, the mux configuration register deter-
mines the conversion type. The register is updated on the
rising edge of WR.
Table 1 lists all conversion options. For example, at
D6/DIFF, a logic 0 or 1 selects a single-ended or differen-
tial conversion. Data is loaded into addressed locations
in the configuration register with a series of WR pulses.
If INH is high while writing, no conversion takes place. A
conversion is started by writing INH = 0 to the configura-
tion register. When a change is made to the contents of
the configuration register, a “dummy” conversion may be
necessary. This is due to a built-in latency of one full con-
version for unipolar/bipolar and single-ended/differential
selections.
It is not necessary to update the configuration register
before every conversion. A particular mux configuration
must be loaded only once after power-up (but the con-
figuration may require several writes to be loaded). A
mux configuration is retained for successive conversions
and during power-down (PD = 1) so that reconfiguring is
unnecessary when the ADC returns to normal operation
(PD = 0). Configuration and RAM data is lost only when
power is removed from the ADC at V
DD
.
When updating the configuration register, INH should be
high for all except the last WR so the conversion is not
started until the mux is set. On WR’s falling edge, all input
channels sample simultaneously. BUSY goes low at the
beginning of the conversion, and channels are converted
sequentially starting with the lowest selected channel.
When BUSY goes high, conversion results are stored
in RAM. At conversion end, a microprocessor (µP) can
access the RAM contents with consecutive RD pulses.
The first accessed data is the lowest channel’s result.
Subsequent RD pulses access conversion results for the
remaining channels.
The configuration data determines which RAM locations
are sequentially read by consecutive RD pulses, so new
data should be placed in the configuration register only
after a full RD operation. It is not necessary to update the
configuration register for every conversion. A new conver-
sion is initiated with a WR pulse (when INH = 0), regard-
less of the number of channe ls that have been read.
Figure 4a shows the MAX155 timing for an 8-channel
unipolar configuration. 8 channels are configured and
8 consecutive RD pulses access data. Figure 4b illus-
trates 4-channel differential conversion timing involving
4 sampled channels and 4 RD pulses. In cases where
conflicting differential configurations are loaded, the last
channel selected with DIFF = 1 will be the positive input
of the differential channel.
Input/Output Mode, Single-Channel Conver-
sion Timing
Figure 5a shows timing for a single-channel (ALL = 1),
single-ended conversion; Figure 5b shows a differential
conversion. With MODE floating, the configuration reg-
ister is updated on the rising edge of WR. BUSY goes
low at the beginning of the conversion and returns high
when the channel designated by the configuration reg-
ister has been converted. All channels are sampled on
the falling edge of WR even if only a single channel has
been requested. At conversion end, the µP can read the
result for the selected channel with a single RD pulse.
Subsequent RD pulses will access old conversion results
remaining in other RAM locations. The next conversion
is initiated with a WR pulse, regardless of the number of
channels that have been read.
INH and A0–A2, in the configuration register, access loca-
tions in RAM. INH = 1 allows the RAM address pointer to
be updated without starting a conversion. A READ pulse
then reads the contents of the addressed location.
MAX155/MAX156 8-/4-Channel ADCs with Simultaneous
T/Hs and Reference
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