Datasheet

MAX15038
Power-Good Output (PWRGD)
PWRGD is an open-drain output that goes high imped-
ance when V
FB
is above 0.925 x V
REFIN
and V
REFIN
is
above 0.54V for at least 48 clock cycles. PWRGD pulls
low when V
FB
is below 90% of V
REFIN
or V
REFIN
is
below 0.54V for at least 48 clock cycles. PWRGD is low
when the IC is in shutdown mode, V
DD
is below the
internal UVLO threshold, or the IC is in thermal shut-
down mode.
Programming the Output Voltage
(CTL1, CTL2)
As shown in Table 1, the output voltage is pin program-
mable by the logic states of CTL1 and CTL2. CTL1 and
CTL2 are trilevel inputs: V
DD
, unconnected, and GND.
An 8.06kΩ resistor must be connected between V
OUT
and FB when CTL1 and CTL2 are connected to GND.
The logic states of CTL1 and CTL2 should be pro-
grammed only before power-up. Once the part is
enabled, CTL1 and CTL2 should not be changed. If the
output voltage needs to be reprogrammed, cycle
power or EN and reprogram before enabling. The out-
put voltage can be programmed continuously from
0.6V to 90% of V
IN
by using a resistor-divider network
from V
OUT
to FB to GND as shown in Figure 3a. CTL1
and CTL2 must be connected to GND.
Shutdown Mode
Drive EN to GND to shut down the IC and reduce quies-
cent current to a typical value of 10µA. During shutdown,
the LX is high impedance. Drive EN high to enable the
MAX15038.
Thermal Protection
Thermal-overload protection limits total power dissipation
in the device. When the junction temperature exceeds
T
J
= +165°C, a thermal sensor forces the device into
shutdown, allowing the die to cool. The thermal sensor
turns the device on again after the junction temperature
cools by 20°C, causing a pulsed output during continu-
ous overload conditions. The soft-start sequence begins
after recovery from a thermal-shutdown condition.
Applications Information
IN and V
DD
Decoupling
To decrease the noise effects due to the high switching
frequency and maximize the output accuracy of
the MAX15038, decouple IN with a 22µF capacitor from
IN to PGND. Also, decouple V
DD
with a 2.2µF
low-ESR ceramic capacitor from V
DD
to GND. Place
these capacitors as close as possible to the IC.
Inductor Selection
Choose an inductor with the following equation:
where LIR is the ratio of the inductor ripple current to full
load current at the minimum duty cycle. Choose LIR
between 20% to 40% for best performance and stability.
Use an inductor with the lowest possible DC resistance
that fits in the allotted dimensions. Powdered iron ferrite
core types are often the best choice for performance.
With any core material, the core must be large enough
not to saturate at the current limit of the MAX15038.
Output-Capacitor Selection
The key selection parameters for the output capacitor
are capacitance, ESR, ESL, and voltage-rating require-
ments. These affect the overall stability, output ripple
voltage, and transient response of the DC-DC convert-
er. The output ripple occurs due to variations in the
charge stored in the output capacitor, the voltage drop
due to the capacitor’s ESR, and the voltage drop due to
the capacitor’s ESL. Estimate the output-voltage ripple
due to the output capacitance, ESR, and ESL:
VV V V
RIPPLE RIPPLE C RIPPLE ESR RIPPLE ESL
=+ +
() ( ) ( ))
L
VVV
fV LIRI
OUT IN OUT
SIN OUTMAX
=
×−
×××
()
()
CTL1 CTL2 V
OUT
(V)
V
OUT
WHEN
USING
EXTERNAL
V
REFIN
(V)
GND GND
0.6* or
0.6 < V
OUT
 0.9 x V
IN
**
V
REFIN
* or
V
REFIN
< V
OUT
 0.9 x V
IN
**
V
DD
V
DD
0.7 V
REFIN
x (7/6)
GND Unconnected 0.8 V
REFIN
x (4/3)
GND V
DD
1.0 V
REFIN
x (5/3)
Unconnected GND 1.2 V
REFIN
x 2
Unconnected Unconnected 1.5 V
REFIN
x 2.5
Unconnected V
DD
1.8 V
REFIN
x 3
V
DD
GND 2.0 V
REFIN
x (10/3)
V
DD
Unconnected 2.5 V
REFIN
x (25/6)
Table 1. CTL1 and CTL2 Output Voltage
Selection
4A, 2MHz Step-Down Regulator
with Integrated Switches
______________________________________________________________________________________ 13
* Install an 8.06k Ω resistor at R3 and do not install a resistor at R4.
** Install R3 and R4 following the equation in the Compensation
Design
section (see Figure 3a).