Datasheet

+2.7V to +5.25V, Low-Power, 8-Channel,
Serial 10-Bit ADCs
MAX148/MAX149
5
TIMING CHARACTERISTICS
(V
DD
= +2.7V to +5.25V, T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
Note 1:
Tested at V
DD
= 2.7V; COM = 0; unipolar single-ended input mode.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 3: MAX149—internal reference, offset nulled; MAX148—external reference (V
REF
= +2.500V), offset nulled.
Note 4: Ground “on” channel; sine wave applied to all “off” channels.
Note 5: Conversion time defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 6: The common-mode range for the analog inputs is from AGND to V
DD
.
Note 7: Sample tested to 0.1% AQL.
Note 8: External load should not change during conversion for specified accuracy.
Note 9: ADC performance is limited by the converter’s noise floor, typically 300FV
P-P
.
Note 10: Guaranteed by design. Not subject to production testing.
Note 11: The MAX148 typically draws 400FA less than the values shown.
Note 12: Measured as |V
FS
(2.7V) - V
FS
(5.25V)|.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Acquisition Time t
ACQ
1.5 μs
DIN to SCLK Setup t
DS
100 ns
DIN to SCLK Hold t
DH
0 ns
SCLK Fall to Output Data Valid t
DO
Figure 1, MAX14_ _C/E 20 200 ns
CS Fall to Output Enable t
DV
Figure 1 240 ns
CS Rise to Output Disable t
TR
Figure 2 240 ns
CS to SCLK Rise Setup t
CSS
100 ns
CS to SCLK Rise Hold t
CSH
0 ns
SCLK Pulse Width High t
CH
200 ns
SCLK Pulse Width Low t
CL
200 ns
SCLK Fall to SSTRB t
SSTRB
Figure 1 240 ns
CS Fall to SSTRB Output Enable t
SDV
External clock mode only, Figure 1 240 ns
CS Rise to SSTRB Output Disable t
STR
External clock mode only, Figure 2 240 ns
SSTRB Rise to SCLK Rise t
SCK
Internal clock mode only (Note 7) 0 ns