Datasheet

315MHz/433MHz ASK Superheterodyne
Receiver with Extended Dynamic Range
Pin Description
PIN
TSSOP TQFN
NAME FUNCTION
1 29 XTAL1 1st Crystal Input. (See the Phase-Locked Loop section.)
2, 7 4, 30 AVDD
Positive Analog Supply Voltage. For +5V operation, pin 2 is the output of an on-chip +3.2V
low-dropout regulator and should be bypassed to AGND with a 0.1µF capacitor as close as
possible to the pin. Pin 7 must be externally connected to the supply from pin 2 and bypassed to
AGND with a 0.01µF capacitor as close as possible to the pin (see the Voltage Regulator section
and the Typical Application Circuit).
3 31 LNAIN Low-Noise Amplifier Input. (See the Low-Noise Amplifier section.)
4 32 LNASRC
Low-Noise Amplifier Source for External Inductive Degeneration. Connect inductor to ground to set
LNA in
p
ut im
p
edance.
(
See the Low-Noise Am
p
lifier section.
)
5 2 AGND Analog Ground
6 3 LNAOUT
Low-Noise Amplifier Output. Connect to mixer through an LC tank filter. (See the Low-Noise
Am
p
lifier section.
)
8 5 MIXIN1 1st Differential Mixer Input. Connect through a 100pF capacitor to V
DD3
side of the LC tank.
9 6 MIXIN2 2nd Differential Mixer Input. Connect through a 100pF capacitor to LC tank filter from LNAOUT.
10 7 AGND Analog Ground
11 8 IRSEL
Im ag e Rej ecti on S el ect P i n. S et V
I RS E L
= 0V to center i m ag e r ej ecti on at 315M H z. Leave IRS E L
unconnected to center i m ag e r ej ecti on at 375M H z. S et V
IRS E L
= V
D D
to center i m ag e r ej ecti on at 433M H z.
12 9 MIXOUT 330Ω Mixer Output. Connect to the input of the 10.7MHz bandpass filter.
13 10 DGND Digital Ground
14 11 DVDD
Positive Digital Supply Voltage. Connect to both of the AVDD pins.
Bypass to DGND with a 0.01µF
capacitor as close as possible to the pin (see the Typical Application Circuit).
15 12 AGCDIS AGC Control Pin. Pull high to disable AGC.
16 14 XTALSEL
Crystal Divider Ratio Select Pin. Drive XTALSEL low to select divider ratio of 64, or drive XTALSEL
high to select divider ratio of 32.
17 15 IFIN1
1st Differential Intermediate Frequency Limiter Amplifier Input. Decouple to AGND with a 1500pF
capacitor.
18 16 IFIN2
2nd Differential Intermediate Frequency Limiter Amplifier Input. Connect to the output of a 10.7MHz
bandpass filter.
19 17 DFO Data Filter Output
20 18 DSN Negative Data Slicer Input
21 19 OPP Noninverting Op-Amp Input for the Sallen-Key Data Filter
22 20 DFFB Data Filter Feedback Node. Input for the feedback of the Sallen-Key data filter.
23 22 DSP Positive Data Slicer Input
24 23 V
DD5
+5V Supply Voltage. Bypass to AGND with a 0.01µF capacitor as close as possible to the pin. For
+5V operation, V
DD5
is the input to an on-chip voltage regulator whose +3.2V output appears at the
pin 2 AVDD pin. (See the Voltage Regulator section and the Typical Application Circuit.)
25 24 DATAOUT Digital Baseband Data Output
26 26 PDOUT Peak Detector Output
27 27 PWRDN Power-Down Select Input. Drive this pin with a logic high to power on the IC.
28 28 XTAL2 2nd Crystal Input
—
1, 13,
21, 25
N.C. No Connection
— — EP Exposed Pad (TQFN Only). Connect EP to GND.
MAX1473
8
Maxim Integrated